Shanthi Pavan - RankMe

140 papers C 25Misc 5Journal 79Unranked 31

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A "Nyquist-Like" Noise Theorem for Linear Periodically-Switched RLC Networks. ISCAS Shanthi Pavan
2025	J	`jnl`	Noise in Periodically-Switched RLC Networks. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2025	J	`jnl`	Weak Nonlinearities in Active Filters and Continuous-Time Pipeline ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Chaitanya Kumar, Shanthi Pavan
2024	J	`jnl`	Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining. IEEE J. Solid State Circuits Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj
2024	J	`jnl`	On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Javad Gorji, Shanthi Pavan, José M. de la Rosa
2024	C	`conf`	Systematic Development of CMOS PTAT Circuits. ISCAS Shanthi Pavan
2023	—	`conf`	A 13.5 mW Decimator for a 20 MHz bandwidth CTΔΣ Modulator using poly-phase decomposition techniques. ICECS Alok Baluni, Shanthi Pavan
2023	C	`conf`	Bandpass $\Delta \Sigma$ Modulators with FIR Feedback. ISCAS Javad Gorji, Shanthi Pavan, José M. de la Rosa
2023	J	`jnl`	Digital Reconstruction in Continuous-Time Pipelined Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Nishanth Basavaraj, Shanthi Pavan
2023	J	`jnl`	Power-Noise Trade-Offs in Continuous-Time Pipelined ADCs and Active Filters. IEEE Trans. Circuits Syst. I Regul. Pap. Chaitanya Kumar, Shanthi Pavan
2023	J	`jnl`	Reciprocity and Inter-Reciprocity: A Tutorial - Part I: Linear Time-Invariant Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Gabor C. Temes
2023	J	`jnl`	Reciprocity and Inter-Reciprocity: A Tutorial - Part II: Linear Periodically Time-Varying Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Gabor C. Temes
2022	—	`conf`	A 0.37mm CICC Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun
2022	J	`jnl`	Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback. IEEE Trans. Circuits Syst. II Express Briefs Raviteja Theertham, Shanthi Pavan
2022	C	`conf`	Analysis of Flash ADC Loading on the Performance of a Continuous-Time Pipelined ADC. ISCAS Chaitanya Kumar, Saravana Manivannan, Shanthi Pavan
2022	J	`jnl`	Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Saravana Manivannan
2022	J	`jnl`	Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs. IEEE J. Solid State Circuits Raviteja Theertham, Satya Narayana Ganta, Shanthi Pavan
2022	J	`jnl`	Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property. IEEE Trans. Circuits Syst. I Regul. Pap. Saravana Manivannan, Shanthi Pavan
2022	J	`jnl`	Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs Nishanth Basavaraj, Saravana Manivannan, Shanthi Pavan
2022	J	`jnl`	Systematic Development of CMOS Fixed-Transconductance Bias Circuits. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2021	C	`conf`	A 28.5µW All-Analog Voice-Activity Detector. ISCAS Udita Mukherjee, Tanmay Halder, Anand Kannan, Sovan Ghosh, Shanthi Pavan
2021	J	`jnl`	Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback. IEEE J. Solid State Circuits Alok Baluni, Shanthi Pavan
2021	J	`jnl`	Continuous-Time Incremental Delta-Sigma Modulators With FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Tanmay Halder, Anand Kannan
2021	J	`jnl`	Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Hajime Shibata
2020	—	`conf`	16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat, Shanthi Pavan
2020	—	`conf`	A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC. CICC Alok Baluni, Shanthi Pavan
2020	J	`jnl`	Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator. IEEE J. Solid State Circuits Sujith Billa, Suhas Dixit, Shanthi Pavan
2020	J	`jnl`	Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density. IEEE J. Solid State Circuits Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan
2020	J	`jnl`	Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering. IEEE Trans. Circuits Syst. Saravana Manivannan, Shanthi Pavan
2020	C	`conf`	Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. ISCAS Raviteja Theertham, Shanthi Pavan
2019	—	`conf`	A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth. VLSI Circuits Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan
2019	—	`conf`	A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth. A-SSCC Sujith Billa, Suhas Dixit, Shanthi Pavan
2019	J	`jnl`	An Alternative Approach to Bode's Noise Theorem. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2019	J	`jnl`	Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Kishalay Datta, Vinod Menezes, Shanthi Pavan
2019	J	`jnl`	Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting. IEEE J. Solid State Circuits Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan
2019	C	`conf`	Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities. ISCAS Saravana Manivannan, Shanthi Pavan
2019	J	`jnl`	Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Raviteja Theertham
2019	C	`conf`	Simplified Analysis of Total Integrated Noise in Passive Switched-Capacitor and N-Path Filters. ISCAS Shanthi Pavan
2019	J	`jnl`	Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Raviteja Theertham, Shanthi Pavan
2018	—	`conf`	A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR. CICC Saravana Manivannan, Shanthi Pavan
2018	J	`jnl`	Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Eric A. M. Klumperink
2018	J	`jnl`	Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. Ankesh Jain, Shanthi Pavan
2018	J	`jnl`	Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities. IEEE Trans. Circuits Syst. I Regul. Pap. Saravana Manivannan, Shanthi Pavan
2018	—	`conf`	Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters. CICC Shanthi Pavan
2018	J	`jnl`	Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Eric A. M. Klumperink
2018	J	`jnl`	Improved Chopping in Continuous-Time Delta-Sigma Converters Using FIR Feedback and N-Path Techniques. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2018	—	`conf`	Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. ESSCIRC Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan
2018	—	`conf`	Practical design and simulation techniques for continuous-time ΔΣ converters. CICC Shanthi Pavan
2018	C	`conf`	What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator? ISCAS Shanthi Pavan, Siddharth Baskaran
2017	J	`jnl`	A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. IEEE J. Solid State Circuits Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan
2017	J	`jnl`	Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping. IEEE J. Solid State Circuits Sujith Billa, Amrith Sukumaran, Shanthi Pavan
2017	J	`jnl`	Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan
2017	J	`jnl`	Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components. IEEE J. Solid State Circuits Neha Sinha, Mansour Rachid, Shanthi Pavan, Sudhakar Pamarti
2017	C	`conf`	On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters. ISCAS Shanthi Pavan
2017	J	`jnl`	Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Eric A. M. Klumperink
2016	—	`conf`	15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. ISSCC Sujith Billa, Amrith Sukumaran, Shanthi Pavan
2016	—	`conf`	A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback. VLSI Circuits Ankesh Jain, Shanthi Pavan
2016	Misc	`conf`	A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition. VLSID Kamlesh Singh, Shanthi Pavan
2016	C	`conf`	Continuous-time ΔΣ modulators with dual switched capacitor resistor DACs. ISCAS Shanthi Pavan
2016	Misc	`conf`	Demystifying Time Varying Circuits and Systems. VLSID Shanthi Pavan, Nagendra Krishnapura
2016	J	`jnl`	Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs. IEEE J. Solid State Circuits Amrith Sukumaran, Shanthi Pavan
2015	C	`conf`	A 10 Gbps eye opening monitor in 65nm CMOS. ISCAS Sandeep Krishnan, Shanthi Pavan
2015	—	`conf`	A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC. ESSCIRC Amrith Sukumaran, Shanthi Pavan
2015	J	`jnl`	Guest Editorial: Next-Generation Delta-Sigma Converters. IEEE J. Emerg. Sel. Topics Circuits Syst. José M. de la Rosa, Richard Schreier, Kong-Pang Pun, Shanthi Pavan
2015	J	`jnl`	Next-Generation Delta-Sigma Converters: Trends and Perspectives. IEEE J. Emerg. Sel. Topics Circuits Syst. José M. de la Rosa, Richard Schreier, Kong-Pang Pun, Shanthi Pavan
2015	J	`jnl`	Outgoing Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan
2015	C	`conf`	Programmable analog pulse shaping for ultra-wideband applications. ISCAS Naga Rajesh, Shanthi Pavan
2014	—	`conf`	29.1 A 5mW CT ΔΣ ADC with embedded 2 ISSCC Radha S. Rajan, Shanthi Pavan
2014	J	`jnl`	Characterization Techniques for High Speed Oversampled Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Ankesh Jain, Shanthi Pavan
2014	J	`jnl`	Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan
2014	J	`jnl`	Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering. IEEE J. Solid State Circuits Radha S. Rajan, Shanthi Pavan
2014	J	`jnl`	Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming. IEEE J. Solid State Circuits Naga Rajesh, Shanthi Pavan
2014	C	`conf`	Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator. ISCAS Shanthi Pavan
2014	J	`jnl`	Guest Editorial Special Section on the 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013). IEEE Trans. Circuits Syst. I Regul. Pap. Yong Lian, Sergios Theodoridis, George Yuan, Shanthi Pavan
2014	J	`jnl`	Incoming Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan
2014	J	`jnl`	Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Radha S. Rajan
2014	J	`jnl`	Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback. IEEE J. Solid State Circuits Amrith Sukumaran, Shanthi Pavan
2014	J	`jnl`	Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Radha S. Rajan
2013	J	`jnl`	A Time-Domain Perspective of the Signal Transfer Function of a Continuous-Time ΔΣ Modulator. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2013	—	`conf`	A lumped component programmable delay element for Ultra-Wideband beamforming. CICC Naga Rajesh, Shanthi Pavan
2013	J	`jnl`	Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC. IEEE J. Solid State Circuits Timir Nandi, Karthikeya Boominathan, Shanthi Pavan
2013	J	`jnl`	Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012). IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Wouter A. Serdijn, Henry Shu-Hung Chung, Ming-Der Shieh, Young Hwan Kim
2013	J	`jnl`	Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012). IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, John W. M. Rogers, Vikas Chandra
2013	C	`conf`	Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface. ISCAS Ankesh Jain, Shanthi Pavan
2012	—	`conf`	A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. ISSCC Pradeep Shettigar, Shanthi Pavan
2012	J	`jnl`	A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. IEEE J. Solid State Circuits Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Debasish Behera, Nimit Nigania
2012	—	`conf`	A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC. CICC Timir Nandi, Karthikeya Boominathan, Shanthi Pavan
2012	J	`jnl`	Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique. IEEE J. Solid State Circuits Ankesh Jain, Muthusubramaniam Venkatesan, Shanthi Pavan
2012	J	`jnl`	Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs. IEEE J. Solid State Circuits Pradeep Shettigar, Shanthi Pavan
2012	J	`jnl`	Device Noise in Continuous-Time Oversampling Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Radha S. Rajan, Shanthi Pavan
2012	C	`conf`	Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs. ISCAS Radha S. Rajan, Shanthi Pavan
2012	J	`jnl`	Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011). IEEE Trans. Circuits Syst. I Regul. Pap. Chip-Hong Chang, Howard C. Luong, Shanthi Pavan
2012	—	`conf`	Little-known features of well-known creatures. ISSCC Un-Ku Moon, Shanthi Pavan
2011	—	`conf`	A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. CICC Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera
2011	—	`conf`	A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range. ESSCIRC Ankesh Jain, Muthusubramanian Venkateswaran, Shanthi Pavan
2011	J	`jnl`	Active-RC Filters Using the Gm-Assisted OTA-RC Technique. IEEE J. Solid State Circuits Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar
2011	J	`jnl`	Alias Rejection of Continuous-Time DeltaSigma Modulators With Switched-Capacitor Feedback DACs. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan
2011	J	`jnl`	On Continuous-Time DeltaSigma Modulators With Return-to-Open DACs. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2011	C	`conf`	The inconvenient truth about alias rejection in continuous time ΔΣ converters. ISCAS Shanthi Pavan
2010	J	`jnl`	Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Vikas Singh, Nagendra Krishnapura, Shanthi Pavan
2010	J	`jnl`	Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan
2010	—	`conf`	Low distortion active filters using the Gm-assisted OTA-RC technique. ESSCIRC Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar
2010	J	`jnl`	Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique. IEEE J. Solid State Circuits Shanthi Pavan, Prabu Sankar
2010	J	`jnl`	Systematic Design Centering of Continuous Time Oversampling Converters. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2010	C	`conf`	Understanding weak loop filter nonlinearities in continuous time ΔΣ converters. ISCAS Shanthi Pavan
2009	—	`conf`	A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range. ESSCIRC Shanthi Pavan, Prabu Sankar
2009	C	`conf`	A Digitally Assisted Baseband Filter with 9MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain. ISCAS Yogesh Darwhekar, Rakesh Kumar, Debapriya Sahu, Shanthi Pavan, Ashish Lachhwani, T. Krishnaswamy, Subhashish Mukherjee
2009	C	`conf`	Automatic Tuning of Time Constants in Single Bit Continuous-time Delta-sigma Modulators. ISCAS Saurabh Saxena, Prabu Sankar, Shanthi Pavan
2009	Misc	`conf`	Negative Feedback System and Circuit Design. VLSI Design Nagendra Krishnapura, Shanthi Pavan
2009	J	`jnl`	Widely Programmable High-Frequency Active IEEE Trans. Circuits Syst. I Regul. Pap. Tonse Laxminidhi, Venkata Prasadu, Shanthi Pavan
2008	—	`conf`	A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range. ESSCIRC Karthikeyan Reddy, Shanthi Pavan
2008	J	`jnl`	A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications. IEEE J. Solid State Circuits Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar
2008	J	`jnl`	Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2008	Misc	`conf`	Oversampling Analog-to-Digital Converter Design. VLSI Design Shanthi Pavan, Nagendra Krishnapura
2008	J	`jnl`	Power and Area-Efficient Adaptive Equalization at Microwave Frequencies. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan
2008	C	`conf`	Power and area efficient high speed analog adaptive equalization. ISCAS Shanthi Pavan
2007	—	`conf`	A 90μW 15-bit ΔΣ ADC for digital audio. ESSCIRC Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar
2007	—	`conf`	A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS. CICC Tonse Laxminidhi, Venkata Prasadu, Shanthi Pavan
2007	J	`jnl`	Accurate Characterization of Integrated Continuous-Time Filters. IEEE J. Solid State Circuits Shanthi Pavan, Tonse Laxminidhi
2007	J	`jnl`	Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Rajesh Tiruvuru
2007	J	`jnl`	Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Prabu Sankar, Shanthi Pavan
2007	J	`jnl`	Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Nagendra Krishnapura
2007	C	`conf`	Design Centering High Frequency Integrated Continuous-Time Filters. ISCAS Tonse Laxminidhi, Shanthi Pavan
2007	J	`jnl`	Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters. IEEE Trans. Circuits Syst. I Regul. Pap. Tonse Laxminidhi, Shanthi Pavan
2007	J	`jnl`	Fundamental Limitations of Continuous-Time Delta-Sigma Modulators Due to Clock Jitter. IEEE Trans. Circuits Syst. I Regul. Pap. Karthikeyan Reddy, Shanthi Pavan
2007	C	`conf`	Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization. ISCAS Shanthi Pavan
2006	J	`jnl`	A Distortion Compensating Flash Analog-to-Digital Conversion Technique. IEEE J. Solid State Circuits Venkata Srinivas, Shanthi Pavan, Ashish Lachhwani, Naga Sasidhar
2006	—	`conf`	A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters. CICC Shanthi Pavan, Tonse Laxminidhi
2006	C	`conf`	Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter. ISCAS Karthikeyan Reddy, Shanthi Pavan
2006	J	`jnl`	Nonidealities in traveling wave and transversal FIR filters operating at microwave frequencies. IEEE Trans. Circuits Syst. I Regul. Pap. Shanthi Pavan, Shankar Shivappa
2006	—	`conf`	Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A. CICC Murali Shanmugasundaram, Shanthi Pavan
2006	Misc	`conf`	System Aspects of Analog to Digital Converter Designs. VLSI Design Shanthi Pavan, Prakash Easwaran, C. Srinivasan
2006	C	`conf`	Transmission line based FIR structures for high speed adaptive equalization. ISCAS Rajesh Tiruvuru, Shanthi Pavan
2005	—	`conf`	Analysis of traveling wave and transversal analog adaptive equalizers. ISCAS (6) Shanthi Pavan, Shankar Shivappa
2004	—	`conf`	A fixed transconductance bias technique for CMOS analog integrated circuits. ISCAS (1) Shanthi Pavan
2004	J	`jnl`	Continuous-time integrated FIR filters at microwave frequencies. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan
2001	—	`conf`	A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. CICC Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan
2000	J	`jnl`	A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid State Circuits Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan
2000	J	`jnl`	Widely programmable high-frequency continuous-time filters in digital CMOS technology. IEEE J. Solid State Circuits Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj
1999	—	`conf`	Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. ISCAS (6) Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj