Shantanu Dutt - RankMe

76 papers A* 3A 15C 4Misc 2Journal 27Unranked 23

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Max Weighted-Matching Based Non-Greedy Post-HLS Power Gating Technique with Comprehensive Power Modeling. ISQED Xiuyan Zhang, Shantanu Dutt
2022	—	`conf`	Limiting Interconnect Heating in Power-Driven Physical Synthesis. SLIP Xiuyan Zhang, Shantanu Dutt
2022	—	`ed.`	Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, SLIP 2022, San Diego, California, 3 November 2022 SLIP Mustafa Badaroglu, Shantanu Dutt
2021	—	`conf`	On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis. ISQED Shantanu Dutt, Xiuyan Zhang, Ouwen Shi
2019	J	`jnl`	A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding. J. Low Power Electron. Xiuyan Zhang, Ouwen Shi, Jian Xu, Shantanu Dutt
2018	A	`conf`	A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis. DATE Shantanu Dutt, Ouwen Shi
2017	—	`conf`	Power-delay product based resource library construction for effective power optimization in HLS. ISQED Shantanu Dutt, Ouwen Shi
2016	J	`jnl`	Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis. J. Low Power Electron. Ouwen Shi, Shantanu Dutt
2015	A	`conf`	Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs. ICCAD Enzo Tartaglione, Shantanu Dutt
2014	J	`jnl`	New Algorithmic Techniques for Complex EDA Problems. VLSI Design Shantanu Dutt, Dinesh P. Mehta, Gi-Joon Nam
2013	J	`jnl`	Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm. VLSI Design Huan Ren, Shantanu Dutt
2011	J	`jnl`	A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement. IEEE Trans. Very Large Scale Integr. Syst. Huan Ren, Shantanu Dutt
2011	J	`jnl`	Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction. IEEE Trans. Very Large Scale Integr. Syst. Shantanu Dutt, Huan Ren
2011	J	`jnl`	Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Huan Ren, Shantanu Dutt
2010	A	`conf`	Timing yield optimization via discrete gate sizing using globally-informed delay PDFs. ICCAD Shantanu Dutt, Huan Ren
2009	—	`conf`	Selection of Multiple SNPs in Case-Control Association Study Using a Discretized Network Flow Approach. BICoB Shantanu Dutt, Yang Dai, Huan Ren, Joel Fontanarosa
2009	J	`jnl`	Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures. ACM Trans. Reconfigurable Technol. Syst. Shantanu Dutt, Li Li
2008	A	`conf`	Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. ICCAD Huan Ren, Shantanu Dutt
2008	J	`jnl`	Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shantanu Dutt, Vinay Verma, Vishal Suthar
2007	J	`jnl`	An efficient delay-optimal distributed termination detection algorithm. J. Parallel Distributed Comput. Nihar R. Mahapatra, Shantanu Dutt
2007	C	`conf`	Constraint satisfaction in incremental placement with application to performance optimization under power constraints. ICCD Huan Ren, Shantanu Dutt
2006	A	`conf`	A network-flow approach to timing-driven incremental placement for ASICs. ICCAD Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar
2006	A	`conf`	Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. DATE Vishal Suthar, Shantanu Dutt
2006	A	`conf`	Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. DATE Shantanu Dutt, Hasan Arslan
2006	Misc	`conf`	Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. VTS Vishal Suthar, Shantanu Dutt
2006	—	`conf`	Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. DFT Federico Rota, Shantanu Dutt, Sahithi Krishna
2005	—	`conf`	High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. ACM Great Lakes Symposium on VLSI Vishal Suthar, Shantanu Dutt
2004	C	`conf`	A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. ICCD Hasan Arslan, Shantanu Dutt
2004	J	`jnl`	Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. Parallel Comput. Nihar R. Mahapatra, Shantanu Dutt
2004	—	`conf`	An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance. ACM Great Lakes Symposium on VLSI Hasan Arslan, Shantanu Dutt
2004	A*	`conf`	Efficient on-line testing of FPGAs with provable diagnosabilities. DAC Vinay Verma, Shantanu Dutt, Vishal Suthar
2004	A	`conf`	Roving testing using new built-in-self-tester designs for FPGAs. FPGA Vinay Verma, Shantanu Dutt
2003	C	`conf`	ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. ICCD Hasan Arslan, Shantanu Dutt
2002	J	`jnl`	A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. ACM Trans. Design Autom. Electr. Syst. Shantanu Dutt, Vinay Verma, Hasan Arslan
2002	A*	`conf`	Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. DAC Ke Zhong, Shantanu Dutt
2002	J	`jnl`	Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. ACM Trans. Design Autom. Electr. Syst. Shantanu Dutt, Wenyong Deng
2001	A	`conf`	A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. ICCAD Vinay Verma, Shantanu Dutt
2001	J	`jnl`	Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. J. Parallel Distributed Comput. Nihar R. Mahapatra, Shantanu Dutt
2000	A	`conf`	Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. ICCAD Ke Zhong, Shantanu Dutt
2000	J	`jnl`	Probability-based approaches to VLSI circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shantanu Dutt, Wenyong Deng
2000	J	`jnl`	Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. Int. J. Found. Comput. Sci. Nihar R. Mahapatra, Shantanu Dutt
1999	—	`conf`	Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. FTCS Nihar R. Mahapatra, Shantanu Dutt
1999	A	`conf`	Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. ICCAD Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger
1999	J	`jnl`	Partitioning using second-order information and stochastic-gainfunctions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shantanu Dutt, Hasan Arslan, Halim Theny
1998	—	`conf`	Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems. IPPS/SPDP Nihar R. Mahapatra, Shantanu Dutt
1998	J	`jnl`	Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. IEEE Trans. Computers Fran Hanchek, Shantanu Dutt
1998	—	`conf`	Partitioning using second-order information and stochastic-gain functions. ISPD Shantanu Dutt, Halim Theny
1997	J	`jnl`	Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. IEEE Trans. Computers Shantanu Dutt, Nihar R. Mahapatra
1997	A	`conf`	Partitioning around roadblocks: tackling constraints with intermediate relaxations. ICCAD Shantanu Dutt, Halim Theny
1997	J	`jnl`	REMOD: a new methodology for designing fault-tolerant arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. Shantanu Dutt, Fran Hanchek
1997	J	`jnl`	Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. IEEE Trans. Parallel Distributed Syst. Nihar R. Mahapatra, Shantanu Dutt
1996	A*	`conf`	A Probability-Based Approach to VLSI Circuit Partitioning. DAC Shantanu Dutt, Wenyong Deng
1996	A	`conf`	Are There Advantages to High-Dimension Architectures? Analysis of International Conference on Supercomputing Shantanu Dutt, Nam Trinh
1996	C	`conf`	Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. ICCD Fran Hancheck, Shantanu Dutt
1996	—	`conf`	Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. FTCS Nihar R. Mahapatra, Shantanu Dutt
1996	J	`jnl`	Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations. IEEE Trans. Computers Shantanu Dutt, Fikri T. Assaad
1996	Misc	`conf`	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. VLSI Design Fran Hanchek, Shantanu Dutt
1996	—	`conf`	Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. IPPS Nihar R. Mahapatra, Shantanu Dutt
1996	A	`conf`	VLSI circuit partitioning by cluster-removal using iterative improvement techniques. ICCAD Shantanu Dutt, Wenyong Deng
1995	—	`conf`	Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. FTCS Shantanu Dutt, Nihar R. Mahapatra
1994	—	`conf`	New Anticipatory Load Balancing Strategies for Parallel A* Algorithms. Parallel Processing of Discrete Optimization Problems Nihar R. Mahapatra, Shantanu Dutt
1994	J	`jnl`	Scalable Load Balancing Strategies for Parallel A* Algorithms. J. Parallel Distributed Comput. Shantanu Dutt, Nihar R. Mahapatra
1993	—	`conf`	Fast Polylog-Time Reconfiguration of Structurally Fault-Tolerant Multiprocessors. SPDP Shantanu Dutt
1993	A	`conf`	New faster Kernighan-Lin-type graph-partitioning algorithms. ICCAD Shantanu Dutt
1993	—	`conf`	Parallel A IPPS Shantanu Dutt, Nihar R. Mahapatra
1993	—	`conf`	Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. SPDP Nihar R. Mahapatra, Shantanu Dutt
1992	—	`conf`	More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication. FTCS Fikri T. Assaad, Shantanu Dutt
1992	J	`jnl`	Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. IEEE Trans. Computers Shantanu Dutt, John P. Hayes
1991	J	`jnl`	Designing Fault-Tolerant System Using Automorphisms. J. Parallel Distributed Comput. Shantanu Dutt, John P. Hayes
1991	—	`conf`	Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. FTCS Shantanu Dutt, John P. Hayes
1991	J	`jnl`	Subcube Allocation in Hypercube Computers. IEEE Trans. Computers Shantanu Dutt, John P. Hayes
1990	—	`—`	Designing and reconfiguring fault-tolerant multiprocessor systems. Shantanu Dutt
1990	J	`jnl`	On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. IEEE Trans. Computers Shantanu Dutt, John P. Hayes
1989	—	`conf`	An automorphic approach to the design of fault-tolerant multiprocessors. FTCS Shantanu Dutt, John P. Hayes
1988	—	`conf`	Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures. FTCS Shantanu Dutt, John P. Hayes
1988	—	`conf`	On allocating subcubes in a hypercube multiprocessor. C³P Shantanu Dutt, John P. Hayes