Shanlin Xiao

53 papers A* 1A 3B 2C 1Misc 3Journal 26Unranked 17
YearRankTypeTitle / Venue / Authors
2026 — conf
An Algorithm-Hardware Co-Design for Efficient and Robust Spiking Neural Networks via Sparsity.
ASP-DAC
Wei Liu, Yinsheng Chen, Jilong Luo, Yusa Wang, Zhiyi Yu, Shanlin Xiao
2026 — conf
Spiking-NeRF: Neural Graphics Acceleration With Spiking Feature Encoding for Edge 3D Rendering.
ASP-DAC
Jianzhen Gao, Wei Liu, Yue Liu, Hengyi Zhou, Zhiyi Yu, Shanlin Xiao
2026 J jnl
SynapseHD: A unified training framework for bridging spiking neural networks and hyperdimensional computing.
Neurocomputing
Lingfeng Zhou, Huiyao Wang, Bohan Wang, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 J jnl
A Hybrid Stochastic-Binary Computing Batch Normalization Engine for Low-Power On-Chip Learning Spiking Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Liu, Yue Liu, Zhiyi Yu, Shanlin Xiao
2025 — conf
A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits.
ISQED
Bohan Wang, Zeyang Xu, Lingfeng Zhou, Huiyao Wang, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 J jnl
ADP-Net: a hierarchical attention-diffusion-prediction framework for human trajectory prediction.
Frontiers Artif. Intell.
Zhenggui Zhang, Shanlin Xiao, Zhiyi Yu
2025 J jnl
ASNA-Flow: An Efficient Asynchronous Neuromorphic Accelerator for Real-Time Event-Based Optical Flow.
IEEE Trans. Very Large Scale Integr. Syst.
Jinghai Wang, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu, Shanlin Xiao
2025 J jnl
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS.
IEEE Trans. Very Large Scale Integr. Syst.
Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu
2025 A conf
Faster-SNN: Towards Faster and Better Spiking Neural Networks with Hybrid Neural Coding.
ICME
Yinsheng Chen, Jilong Luo, Zhiyi Yu, Shanlin Xiao
2025 — conf
Fine-Grained Recognition of Arteriovenous Fistula Stenosis Using Blood Flow Sounds: An Animal Model-Based Dataset and a Frequency-Aware Decoupling Network.
ICANN (4)
Shanlin Xiao, Yangyi Zhou, Jie Zhu, Jincen Wang, Yan Zhao, Yuan Zong, Jie Kong
2025 — conf
SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks.
ASP-DAC
Bo Li, Yue Liu, Wei Liu, Jinghai Wang, Xiao Huang, Zhiyi Yu, Shanlin Xiao
2025 A conf
Stair-LIF: Boosting the Representation of Spiking Neural Networks with Learnable Incremental Multi-Threshold Neurons.
ICME
Jilong Luo, Yinsheng Chen, Yue Liu, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 A* conf
Towards In-Situ Neuromorphic Computing Architecture for Event Stream Super-Resolution.
DAC
Yihe Yu, Bo Li, Kexin Huang, Wei Liu, Jinghai Wang, Yue Liu, Zhiyi Yu, Shanlin Xiao
2025 Misc conf
Unsupervised Motion-Robust Self-Distillation Framework for Remote Physiological Measurement.
ICASSP
Anbang Liu, Shanlin Xiao, Wenming Zheng
2024 A conf
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint.
DATE
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 — conf
An FPGA-based QDI Asynchronous Circuits Design Methodology.
ICTA
Guangyao Lin, Jinghai Wang, Zeyang Xu, Zhiyi Yu, Shanlin Xiao
2024 J jnl
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension.
IEEE Trans. Very Large Scale Integr. Syst.
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 — conf
Energy-Efficient and Fault-Tolerant Sparse Coding for Spiking Neural Networks Accelerator.
ICTA
Bo Li, Wei Liu, Yue Liu, Xiao Huang, Zhiyi Yu, Shanlin Xiao
2024 J jnl
LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift.
IEEE Trans. Circuits Syst. II Express Briefs
Huiyao Wang, Shanlin Xiao, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 J jnl
SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule.
IEEE Trans. Biomed. Circuits Syst.
Wei Liu, Shanlin Xiao, Yue Liu, Zhiyi Yu
2024 Misc conf
Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer.
ICASSP
Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu
2024 J jnl
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint.
IEEE Trans. Very Large Scale Integr. Syst.
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2023 J jnl
Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks.
CoRR
Jilong Luo, Shanlin Xiao, Yinsheng Chen, Zhiyi Yu
2023 J jnl
SparseSpikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer.
CoRR
Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu
2023 — conf
Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient.
ICTA
Kexin Huang, Wei Liu, Yue Liu, Shanlin Xiao, Zhiyi Yu
2023 — conf
Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement.
ICTA
Zeyang Xu, Shanlin Xiao, Lingfeng Zhou, Bohan Wang, Zhiyi Yu
2022 J jnl
A dual-rail/single-rail hybrid system using null convention logic circuits.
Microelectron. J.
Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu
2022 J jnl
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Yuhao Huang, Shanlin Xiao, Zhiyu Li, Zhiyi Yu
2022 — conf
DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits.
ICTA
Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu
2021 Misc conf
3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA.
FCCM
Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu
2021 J jnl
A Data-Driven Asynchronous Neural Network Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shanlin Xiao, Weikun Liu, Junshu Lin, Zhiyi Yu
2021 J jnl
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method.
IEEE Trans. Circuits Syst. II Express Briefs
Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, Zhiyi Yu
2021 — conf
A high throughput spatially coupled low density generator matrix coding system.
ICTA
Ziyuan Luo, Qingyi Xie, Shanlin Xiao, Zhiyi Yu
2021 J jnl
Balancing the Cost and Performance Trade-Offs in SNN Processors.
IEEE Trans. Circuits Syst. II Express Briefs
Huanliang Zheng, Yuhao Guo, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2021 J jnl
Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks.
IEICE Electron. Express
Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu
2021 — conf
FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs.
ICTA
Jian Wang, Huipeng Deng, Huafeng Ye, Shanlin Xiao, Zhiyi Yu
2021 J jnl
Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing.
J. Electronic Imaging
Qiang Zhang, Shanlin Xiao, Zhiyi Yu, Huanliang Zheng, Peng Wang
2021 — conf
High-Throughput Zipper Encoder for 800G Optical Communication System.
ICTA
Qingyi Xie, Ziyuan Luo, Shanlin Xiao, Kai Wang, Zhiyi Yu
2021 J jnl
High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning.
Neurocomputing
Mingyuan Meng, Xingyu Yang, Lei Bi, Jinman Kim, Shanlin Xiao, Zhiyi Yu
2020 C conf
A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection.
ISCAS
Wenkang Liao, Yuhao Guo, Shanlin Xiao, Zhiyi Yu
2020 — conf
A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs.
ICTA
Weikun Liu, Junshu Lin, Xusheng Li, Shanlin Xiao, Zhiyi Yu
2020 — conf
An Asynchronous Convolution Process Engine forVGG-16 Neural Network.
ICTA
Junshu Lin, Weikun Liu, Xusheng Li, Shanlin Xiao, Zhiyi Yu
2020 J jnl
BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network.
CoRR
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2020 J jnl
Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing.
IEEE Trans. Biomed. Circuits Syst.
Shanlin Xiao, Wei Liu, Yuhao Guo, Zhiyi Yu
2020 J jnl
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li, Zhiyi Yu
2020 B conf
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs.
ICPR
Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu
2020 J jnl
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs.
CoRR
Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu
2020 B conf
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks.
IJCNN
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2020 J jnl
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks.
CoRR
Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu
2018 — conf
A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration.
APSIPA
Xiaobai Chen, Shanlin Xiao, Zhiyi Yu
2017 J jnl
Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda
2017 J jnl
HOG-Based Object Detection Processor Design Using ASIP Methodology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda
2016 — conf
An efficient embedded processor for object detection using ASIP methodology.
ASAP
Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda