Shankar Balachandran

41 papers A* 3A 3B 7C 4Misc 4Journal 14Unranked 6

Year	Rank	Type	Title / Venue / Authors
2022	A*	`conf`	Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction. MICRO Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, Onur Mutlu
2022	J	`jnl`	Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction. CoRR Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, Onur Mutlu
2021	A*	`conf`	REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute. ISCA Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney
2020	B	`conf`	Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. ISPASS Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney
2020	J	`jnl`	Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute. CoRR Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney
2018	J	`jnl`	CHOAMP: Cost Based Hardware Optimization for Asymmetric Multicore Processors. IEEE Trans. Multi Scale Comput. Syst. Jyothi Krishna Viswakaran Sreelatha, Shankar Balachandran, Rupesh Nasre
2018	J	`jnl`	Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors. CoRR Jyothi Krishna V. S, Shankar Balachandran
2016	J	`jnl`	Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers. IEEE Comput. Archit. Lett. Biswabandan Panda, Shankar Balachandran
2016	Misc	`conf`	Subclasses of Baxter Permutations Based on Pattern Avoidance. CSR Shankar Balachandran, Sajin Koroth
2015	Misc	`conf`	A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement. VLSID B. N. Bhramar Ray, Shankar Balachandran
2015	—	`conf`	A Soft Error Resilient Low Leakage SRAM Cell Design. ATS Adithyalal P. M, Shankar Balachandran, Virendra Singh
2015	C	`conf`	Application behavior aware re-reference interval prediction for shared LLC. ICCD Parth Lathigara, Shankar Balachandran, Virendra Singh
2015	J	`jnl`	CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores. ACM Trans. Archit. Code Optim. Biswabandan Panda, Shankar Balachandran
2015	J	`jnl`	Fast-SL: an efficient algorithm to identify synthetic lethal sets in metabolic networks. Bioinform. Aditya Pratapa, Shankar Balachandran, Karthik Raman
2015	J	`jnl`	ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti
2014	—	`conf`	CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus. INA-OCMC@HiPEAC Nihar Rathod, Shankar Balachandran, Neel Gala
2014	A	`conf`	Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control. DATE Biswabandan Panda, Shankar Balachandran
2014	J	`jnl`	XStat: Statistical J. Low Power Electron. Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti
2014	B	`conf`	XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs. PACT Biswabandan Panda, Shankar Balachandran
2013	A	`conf`	An efficient wirelength model for analytical placement. DATE B. N. Bhramar Ray, Shankar Balachandran
2013	A	`conf`	CUPL: a compile-time uncoalesced memory access pattern locator for CUDA. ICS Madhur Amilkanthwar, Shankar Balachandran
2013	C	`conf`	LPScan: An algorithm for supply scaling and switching activity minimization during test. ICCD Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran
2013	Misc	`conf`	Measuring Area-Complexity Using Boolean Difference. VLSI Design Ankit Kagliwal, Shankar Balachandran
2013	B	`conf`	TCPT - Thread criticality-driven prefetcher throttling. PACT Biswabandan Panda, Shankar Balachandran
2012	C	`conf`	Augmentation of Programs with CUDA Streams. ISPA Sharmistha, Madhur Amilkanthwar, Shankar Balachandran
2012	C	`conf`	CSHARP: Coherence and SHaring Aware Cache Replacement Policies for Parallel Applications. SBAC-PAD Biswabandan Panda, Shankar Balachandran
2012	B	`conf`	Hardware prefetchers for emerging parallel applications. PACT Biswabandan Panda, Shankar Balachandran
2012	Misc	`conf`	Set-Cover Heuristics for Two-Level Logic Minimization. VLSI Design Ankit Kagliwal, Shankar Balachandran
2012	—	`conf`	The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency. HotPower Ashok Gautham, Kunal Korgaonkar, Patanjali SLPSK, Shankar Balachandran, Kamakoti Veezhinathan
2011	J	`jnl`	24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. J. Low Power Electron. Nitin Chandrachoodan, Shankar Balachandran
2011	—	`conf`	A New Wirelength Model for Analytical Placement. ISVLSI B. N. Bhramar Ray, Shankar Balachandran
2011	J	`jnl`	A Study on Hierarchical Floorplans of Order k CoRR Shankar Balachandran, Sajin Koroth
2011	J	`jnl`	A study on the number of Hierarchical Rectangular Partitions of Order k CoRR Shankar Balachandran, Sajin Koroth
2005	J	`jnl`	A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shankar Balachandran, Dinesh Bhatia
2005	B	`conf`	Timing Aware Interconnect Prediction Models for FPGAs. FPL Shankar Balachandran, Dinesh Bhatia
2004	J	`jnl`	On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
2003	—	`conf`	A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP Shankar Balachandran, Dinesh Bhatia
2002	—	`conf`	On Routing Demand and Congestion Estimation for FPGAs. ASP-DAC/VLSI Design Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
2002	A*	`conf`	On metrics for comparing routability estimation methods for FPGAs. DAC PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
2002	B	`conf`	Rapid and Reliable Routability Estimation for FPGAs. FPL PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
2001	B	`conf`	fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia