Shang Liu - RankMe

23 papers A* 3A 4B 1Journal 11Unranked 4

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A New Benchmark for the Appropriate Evaluation of RTL Code Optimization. CoRR Yao Lu, Shang Liu, Hangan Zhou, Wenji Fang, Qijun Zhang, Zhiyao Xie
2026	—	`conf`	ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. ASP-DAC Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie
2025	—	`conf`	A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. ASP-DAC Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2025	—	`conf`	AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. ASP-DAC Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2025	A	`conf`	GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment. ICCAD Wenji Fang, Wang Jing, Yao Lu, Shang Liu, Zhiyao Xie
2025	A	`conf`	HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions. ICCAD Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie
2025	A*	`conf`	NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. DAC Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. CoRR Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2025	J	`jnl`	ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. CoRR Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie
2025	A*	`conf`	SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. DAC Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie
2025	J	`jnl`	SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. CoRR Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie
2025	—	`conf`	Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. ASP-DAC Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie
2025	J	`jnl`	Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2024	A*	`conf`	Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	J	`jnl`	Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	J	`jnl`	AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2024	J	`jnl`	AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie
2024	A	`conf`	OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. ICCAD Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie
2024	B	`conf`	RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. ASPDAC Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie
2023	A	`conf`	MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023	J	`jnl`	MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023	J	`jnl`	RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie