Shane T. Fleming

19 papers A* 1A 4B 4C 1Misc 1Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2024 J jnl
Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC.
IEEE Trans. Computers
Junyi Liu, Aleksandar Dragojevic, Shane T. Fleming, Antonios Katsarakis, Dario Korolija, Igor Zablotchi, Ho-Cheung Ng, Anuj Kalia, Miguel Castro
2023 J jnl
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture.
ACM Trans. Parallel Comput.
Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming
2022 J jnl
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code.
IEEE Trans. Computers
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides
2021 C conf
General hardware multicasting for fine-grained message-passing architectures.
PDP
Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2020 — conf
Termination detection for fine-grained message-passing architectures.
ASAP
Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2019 B conf
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes.
FPL
Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
2019 A conf
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code.
FPGA
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides
2018 — conf
Accelerating Top-k ListNet Training for Ranking Using FPGA.
FPT
Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
2018 — conf
Injecting FPGA Configuration Faults in Parallel.
FPT
Shane T. Fleming, David B. Thomas
2017 A conf
Hardware Synthesis of Weakly Consistent C Concurrency.
FPGA
Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides
2017 Misc conf
Using Runahead Execution to Hide Memory Latency in High Level Synthesis.
FCCM
Shane T. Fleming, David B. Thomas
2016 A* conf
StitchUp: automatic control flow protection for high level synthesis circuits.
DAC
Shane T. Fleming, David B. Thomas
2015 B conf
PushPush: Seamless integration of hardware and software objects via function calls over AXI.
FPL
Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica
2015 A conf
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System.
FPGA
Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica
2015 A conf
Transparent linking of compiled software and synthesized hardware.
DATE
David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica
2014 B conf
Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs.
FPL
Shane T. Fleming, David B. Thomas
2014 — conf
Is high level synthesis ready for business? A computational finance case study.
FPT
Gordon Inggs, Shane T. Fleming, David B. Thomas, Wayne Luk
2013 B conf
FPGA based control for real time systems.
FPL
Shane T. Fleming, David B. Thomas
2013 — conf
Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields.
ARC
Shane T. Fleming, David B. Thomas