Shaishav Desai

13 papers C 1Journal 2Unranked 10
YearRankTypeTitle / Venue / Authors
2026 — conf
A 0.23pJ/b 24Gb/s Modular D2D Interface with Zero Wake Penalty Clock Gating in 3nm.
ISSCC
Ravi Shivnaraine, Charles Boecker, Eric Groen, Simon Li, Ping Lu, Socrates D. Vamvakos, Roxanne Vu, Chris Hanke, Shankar Tangirala, Wen Liu, Marina Salik, Kevin Bartholomew, Sushmitha Reddy, Alex Tessitore, Aws Shallal, Kalyan Nallaparaju, Jin Liang, Minhan Chen, Shaishav Desai
2024 C conf
A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC.
ISCAS
Ping Lu, Minhan Chen, Shaishav Desai
2022 — conf
An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications.
MWSCAS
Ping Lu, Minhan Chen, Shaishav Desai
2021 J jnl
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.
IEEE J. Solid State Circuits
Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Kulwant Brar, Nhat Nguyen, Shaishav Desai
2021 J jnl
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.
IEEE J. Solid State Circuits
Haidang Lin, Charlie Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Kulwant Brar, Nhat Nguyen, Shaishav Desai
2020 — conf
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.
ISSCC
Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Nhat Nguyen, Shaishav Desai
2020 — conf
A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET.
VLSI Circuits
Haidang Lin, Charles Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Nhat Nguyen, Shaishav Desai
2014 — conf
A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop.
CICC
Socrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung
2012 — conf
A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications.
MWSCAS
Socrates D. Vamvakos, Claude R. Gauthier, Chethan Rao, Karthisha Ramoshan Canagasaby, Prashant Choudhary, Sanjay Dabral, Shaishav Desai, Mahmudul Hassan, Kuo-Chiang Hsieh, Bendik Kleveland, Gurupada Mandal, Richard Rouse, Ritesh Saraf, Alvin Wang, Jason Yeung, Khaldoon Abugharbieh, Ying Cao
2012 — conf
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency.
ESSCIRC
Socrates D. Vamvakos, Bendik Kleveland, Dipak K. Sikdar, B. K. Ahuja, Haidang Lin, Jayaprakash Balachandran, Wignes Balakrishnan, Aldo Bottelli, Jawji Chen, Xiaole Chen, Jae Choi, Jeong Choi, Rajesh Chopra, Sanjay Dabral, Kalyan Dasari, Ronald B. David, Shaishav Desai, Claude R. Gauthier, Mahmudul Hassan, Kuo-Chiang Hsieh, Ramosan Canagasaby, Jeff Kumala, E. P. Kwon, Ben Lee, Ming Liu, Gurupada Mandal, Sundari Mitra, Byeong Cheol Na, Siddharth Panwar, Jay Patel, Chethan Rao, Vithal Rao, Richard Rouse, Ritesh Saraf, Subramanian Seshadri, Jae-K. Sim, Clement Szeto, Alvin Wang, Jason Yeung
2009 — conf
A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes.
CICC
Chethan Rao, Alvin Wang, Shaishav Desai
2007 — conf
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems.
ISSCC
Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong
2007 — conf
A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process.
ISSCC
Shaishav Desai, Pradeep Trivedi, Vincent Von Kanael