Shahrzad Mirkhani

22 papers A* 2A 4C 2Misc 2Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
CLEAR Cross-Layer Resilience: A Retrospective.
IEEE Des. Test
Eric Cheng, Hyungmin Cho, Shahrzad Mirkhani, Lukasz G. Szafaryn, Jacob A. Abraham, Pradip Bose, Chen-Yong Cher, Klas Lilja, Kevin Skadron, Mircea Stan, Subhasish Mitra
2019 — conf
Computational Storage For Big Data Analytics.
ADMS@VLDB
Balavinayagam Samynathan, Keith Chapman, Mehdi Nik, Behnam Robatmili, Shahrzad Mirkhani, Maysam Lavasani
2018 J jnl
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2017 C conf
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
ICCD
Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra
2017 J jnl
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
CoRR
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2016 J jnl
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores.
CoRR
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2016 A* conf
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
DAC
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2015 A conf
Efficient soft error vulnerability estimation of complex designs.
DATE
Shahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher, Jacob A. Abraham
2015 Misc conf
In-depth soft error vulnerability analysis using synthetic benchmarks.
VTS
Shahrzad Mirkhani, Balavinayagam Samynathan, Jacob A. Abraham
2014 A conf
EAGLE: A regression model for fault coverage estimation using a simulation based metric.
ITC
Shahrzad Mirkhani, Jacob A. Abraham
2014 Misc conf
Fast evaluation of test vector sets using a simulation-based statistical metric.
VTS
Shahrzad Mirkhani, Jacob A. Abraham
2014 — conf
Rethinking error injection for effective resilience.
ASP-DAC
Shahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham
2013 A* conf
Quantitative evaluation of soft error injection techniques for robust system design.
DAC
Hyungmin Cho, Shahrzad Mirkhani, Chen-Yong Cher, Jacob A. Abraham, Subhasish Mitra
2012 A conf
FALCON: Rapid statistical fault coverage estimation for complex designs.
ITC
Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow
2007 C conf
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.
FDL
Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi
2007 — conf
RT level reliability enhancement by constructing dynamic TMRS.
ACM Great Lakes Symposium on VLSI
Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi
2006 — conf
ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs.
ATS
Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi
2005 — conf
Enhancing Fault Simulation Performance by Dynamic Fault Clustering.
Asian Test Symposium
Shahrzad Mirkhani, Zainalabedin Navabi
2004 J jnl
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electron. Test.
Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi
2002 — conf
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.
Asian Test Symposium
Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi
2001 A conf
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.
DATE
Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
2001 — conf
Fault Simulation for VHDL Based Test Bench and BIST Evaluation.
Asian Test Symposium
Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi