Shahar Kvatinsky

145 papers A* 5A 7B 3C 15Misc 1Journal 87Unranked 24

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Comparative Study of Digital Memristor-Based Processing-In-Memory from a Device and Reliability Perspective. CoRR Thomas Neuner, Henriette Padberg, Lior Kornblum, Eilam Yalon, Pedram Khalili Amiri, Shahar Kvatinsky
2025	J	`jnl`	A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Li, Yijun Cui, Chongyan Gu, Chenghua Wang, Weiqiang Liu, Shahar Kvatinsky
2025	B	`conf`	Dependable Neuromorphic Computing-in-Memory Architectures. ETS Farhad Merchant, Ankit Bende, Markus Fritscher, Shahar Kvatinsky, Simranjeet Singh, Vikas Rana, Regina Dittmann, Keerthi Dorai Swamy Reddy, Christian Wenger, Fouwad Jamil Mir, Mottaqiallah Taouil, Manil Dev Gomony, Said Hamdioui, Henk Corporaal
2025	—	`conf`	Preprocessing Methods for Memristive Reservoir Computing for Image Recognition. MetroXRAINE Rishona Daniels, Duna Wattad, Ronny Ronen, David Saad, Shahar Kvatinsky
2025	J	`jnl`	Preprocessing Methods for Memristive Reservoir Computing for Image Recognition. CoRR Rishona Daniels, Duna Wattad, Ronny Ronen, David Saad, Shahar Kvatinsky
2025	—	`ed.`	Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025 - 2 July 2025 ACM Great Lakes Symposium on VLSI Lu Peng, Boris Vaisband, Fan Chen, Peipei Zhou, Shahar Kvatinsky, Jiafeng Xie
2025	—	`conf`	Stateful Logic In-Memory Using Gain-Cell eDRAM. NewCAS Barak Hoffer, Shahar Kvatinsky
2025	J	`jnl`	Stateful Logic In-Memory Using Gain-Cell eDRAM. CoRR Barak Hoffer, Shahar Kvatinsky
2024	A	`conf`	A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing. DATE Jiang Li, Yijun Cui, Chenghua Wang, Weiqiang Liu, Shahar Kvatinsky
2024	J	`jnl`	A Pipelined Memristive Neural Network Analog-to-Digital Converter. CoRR Loai Danial, Kanishka Sharma, Shahar Kvatinsky
2024	J	`jnl`	Accelerating DNA Read Mapping with Digital Processing-in-Memory. CoRR Rotem Ben Hur, Orian Leitersdorf, Ronny Ronen, Lidor Goldshmidt, Idan Magram, Lior Kaplun, Leonid Yavitz, Shahar Kvatinsky
2024	C	`conf`	Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays. ISCAS Arjun Tyagi, Shahar Kvatinsky
2024	J	`jnl`	Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays. CoRR Arjun Tyagi, Shahar Kvatinsky
2024	Misc	`conf`	Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. VLSID Noa Aflalo, Eilam Yalon, Shahar Kvatinsky
2024	J	`jnl`	Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. CoRR Noa Aflalo, Eilam Yalon, Shahar Kvatinsky
2024	J	`jnl`	Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism Memristors. IEEE Trans. Circuits Syst. II Express Briefs Henriette Padberg, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas, Jean-Francois Nodin, Shahar Kvatinsky
2024	J	`jnl`	IMPACT:InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference. CoRR Omar Ghazal, Wei Wang, Shahar Kvatinsky, Farhad Merchant, Alex Yakovlev, Rishad A. Shafik
2024	A*	`conf`	PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors. MICRO Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2024	J	`jnl`	Roadmap to Neuromorphic Computing with Emerging Technologies. CoRR Adnan Mehonic, Daniele Ielmini, Kaushik Roy, Onur Mutlu, Shahar Kvatinsky, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Sabina Spiga, Sergey Savelev, Alexander G. Balanov, Nitin Chawla, Giuseppe Desoli, Gerardo Malavena, Christian Monzio Compagnoni, Zhongrui Wang, J. Joshua Yang, Syed Ghazi Sarwat, Abu Sebastian, Thomas Mikolajick, Beatriz Noheda, Stefan Slesazeck, Bernard Dieny, Tuo-Hung Hou, Akhil Varri, Frank Brückerhoff-Plückelmann, Wolfram H. P. Pernice, Xixiang Zhang, Sebastian Pazos, Mario Lanza, Stefan Wiefels, Regina Dittmann, Wing H. Ng, Mark Buckwell, Horatio Cox, Daniel J. Mannion, Anthony J. Kenyon, Yingming Lu, Yuchao Yang, Damien Querlioz, Louis Hutin, Elisa Vianello, Sayeed Shafayet Chowdhury, Piergiulio Mannocci, Yimao Cai, Zhong Sun, Giacomo Pedretti, John Paul Strachan, Dmitri B. Strukov, Manuel Le Gallo, Stefano Ambrogio, Ilia Valov, Rainer Waser
2024	J	`jnl`	TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minhui Zou, Zhenhua Zhu, Tzofnat Greenberg-Toledo, Orian Leitersdorf, Jiang Li, Junlong Zhou, Yu Wang, Nan Du, Shahar Kvatinsky
2024	J	`jnl`	Transimpedance Amplifier with Automatic Gain Control Based on Memristors for Optical Signal Acquisition. CoRR Sariel Hodisan, Shahar Kvatinsky
2024	J	`jnl`	Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. IEEE Trans. Emerg. Top. Comput. Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
2024	J	`jnl`	VVTEAM: A Compact Behavioral Model for Volatile Memristors. CoRR Tanay Patni, Rishona Daniels, Shahar Kvatinsky
2023	—	`conf`	Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. NEWCAS Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. CoRR Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	An Asynchronous and Low-Power True Random Number Generator using STT-MTJ. CoRR Ben Perach, Shahar Kvatinsky
2023	J	`jnl`	AritPIM: High-Throughput In-Memory Arithmetic. IEEE Trans. Emerg. Top. Comput. Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory. CoRR Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
2023	J	`jnl`	ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. IEEE Trans. Very Large Scale Integr. Syst. Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
2023	J	`jnl`	ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2023	—	`conf`	Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. SOCC Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. CoRR Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	Experimental Demonstration of Non-Stateful In-Memory Logic with 1T1R OxRAM Valence Change Mechanism Memristors. CoRR Henriette Padberg, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas, Jean-François Nodin, Shahar Kvatinsky
2023	J	`jnl`	FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication. CoRR Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky
2023	A*	`conf`	On Consistency for Bulk-Bitwise Processing-in-Memory. HPCA Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	TDPP: Two-Dimensional Permutation-Based Protection of Memristive Deep Neural Networks. CoRR Minhui Zou, Zhenhua Zhu, Tzofnat Greenberg-Toledo, Orian Leitersdorf, Jiang Li, Junlong Zhou, Yu Wang, Nan Du, Shahar Kvatinsky
2022	J	`jnl`	AritPIM: High-Throughput In-Memory Arithmetic. CoRR Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory. CoRR Mor M. Dahan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick, Shahar Kvatinsky
2022	J	`jnl`	C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Mor M. Dahan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick, Shahar Kvatinsky
2022	J	`jnl`	Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. Adv. Intell. Syst. Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky
2022	J	`jnl`	Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. CoRR Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky
2022	—	`conf`	Enhancing Security of Memristor Computing System Through Secure Weight Mapping. ISVLSI Minhui Zou, Junlong Zhou, Xiaotong Cui, Wei Wang, Shahar Kvatinsky
2022	J	`jnl`	Enhancing Security of Memristor Computing System Through Secure Weight Mapping. CoRR Minhui Zou, Junlong Zhou, Xiaotong Cui, Wei Wang, Shahar Kvatinsky
2022	J	`jnl`	FiltPIM: In-Memory Filter for DNA Sequencing. CoRR Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
2022	—	`conf`	HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. MOCAST Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. CoRR Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	Making Real Memristive Processing-in-Memory Faster and Reliable. CoRR Shahar Kvatinsky
2022	C	`conf`	MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. ISCAS Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	Memristive deep belief neural network by silicon synapses. CoRR Wei Wang, Loai Danial, Yang Li, Eric Herbelin, Evgeny Pikhay, Yakov Roizin, Barak Hoffer, Zhongrui Wang, Shahar Kvatinsky
2022	J	`jnl`	MultPIM: Fast Stateful Multiplication for Processing-in-Memory. IEEE Trans. Circuits Syst. II Express Briefs Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	On Consistency for Bulk-Bitwise Processing-in-Memory. CoRR Ben Perach, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. CoRR Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
2022	J	`jnl`	PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM. CoRR Barak Hoffer, Shahar Kvatinsky
2022	J	`jnl`	Physical based compact model of Y-Flash memristor for neuromorphic computation. CoRR Wei Wang, Loai Danial, Eric Herbelin, Barak Hoffer, Batel Oved, Tzofnat Greenberg-Toledo, Evgeny Pikhay, Yakov Roizin, Shahar Kvatinsky
2022	J	`jnl`	Review of security techniques for memristor computing systems. CoRR Minhui Zou, Nan Du, Shahar Kvatinsky
2022	J	`jnl`	Stateful Logic using Phase Change Memory. CoRR Barak Hoffer, Nicolás Wainstein, Christopher M. Neumann, Eric Pop, Eilam Yalon, Shahar Kvatinsky
2022	J	`jnl`	Superconductive Logic Using 2ϕ - Josephson Junctions With Half Flux Quantum Pulses. IEEE Trans. Circuits Syst. II Express Briefs Issa Salameh, Eby G. Friedman, Shahar Kvatinsky
2022	J	`jnl`	The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. ACM J. Emerg. Technol. Comput. Syst. Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2022	—	`conf`	Undergraduate Students' Attitudes Toward an Engineering Course that Integrates Several Levels of Abstraction. ICL (2) Aharon Gero, Mohammed Ali Hadish, Shahar Kvatinsky
2022	J	`jnl`	abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. CoRR Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	(V)TEAM for SPICE Simulation of Memristive Devices With Improved Numerical Performance. IEEE Access Dalibor Biolek, Zdenek Kolka, Viera Biolková, Zdenek Biolek, Shahar Kvatinsky
2021	A*	`conf`	Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. DAC Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. CoRR Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2021	—	`conf`	FiltPIM: In-Memory Filter for DNA Sequencing. ICECS Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
2021	J	`jnl`	Improving Efficiency and Lifetime of Logic-in-Memory by Combining IMPLY and MAGIC Families. J. Syst. Archit. Minhui Zou, Junlong Zhou, Jin Sun, Chengliang Wang, Shahar Kvatinsky
2021	—	`conf`	Making Memristive Processing-in-Memory Reliable. ICECS Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	Making Memristive Processing-in-Memory Reliable. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	MultPIM: Fast Stateful Multiplication for Processing-in-Memory. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	Radiofrequency Switches Based on Emerging Resistive Memory Technologies - A Survey. Proc. IEEE Nicolás Wainstein, Gina C. Adam, Eilam Yalon, Shahar Kvatinsky
2021	J	`jnl`	The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. CoRR Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2021	—	`ed.`	VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis
2021	J	`jnl`	multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2020	C	`conf`	A Pipelined Memristive Neural Network Analog-to-Digital Converter. ISCAS Loai Danial, Kanishka Sharma, Shahar Kvatinsky
2020	C	`conf`	An Asynchronous and Low-Power True Random Number Generator using STT-MTJ. ISCAS Ben Perach, Shahar Kvatinsky
2020	—	`conf`	Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters. ECCTD Loai Danial, Shahar Kvatinsky
2020	A	`conf`	CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ICCAD Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky
2020	J	`jnl`	CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. CoRR Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky
2020	J	`jnl`	Cytomorphic Electronics With Memristors for Modeling Fundamental Genetic Circuits. IEEE Trans. Biomed. Circuits Syst. Hanna Abo Hanna, Loai Danial, Shahar Kvatinsky, Ramez Daniel
2020	A	`conf`	Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing. DATE Loai Danial, Vasu Gupta, Evgeny Pikhay, Yakov Roizin, Shahar Kvatinsky
2020	J	`jnl`	SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rotem Ben Hur, Ronny Ronen, Ameer Haj Ali, Debjyoti Bhattacharjee, Adi Eliahu, Natan Peled, Shahar Kvatinsky
2020	—	`conf`	Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. DFT Vishal Gupta, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi
2020	C	`conf`	X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. VLSI-SOC Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2020	—	`conf`	abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. VLSI-SoC (Selected Papers) Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2020	C	`conf`	abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. VLSI-SOC Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2019	—	`conf`	A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors. ISVLSI Nicolás Wainstein, Tamir Tsabari, Yarden Goldin, Eilam Yalon, Shahar Kvatinsky
2019	C	`conf`	A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. VLSI-SoC João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
2019	J	`jnl`	A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Edouard Giacomin, Tzofnat Greenberg-Toledo, Shahar Kvatinsky, Pierre-Emmanuel Gaillardon
2019	—	`ch.`	A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2019	—	`conf`	Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. VLSI-SoC (Selected Papers) João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
2019	J	`jnl`	Adaptive programming in multi-level cell ReRAM. Microelectron. J. Misbah Ramadan, Nicolás Wainstein, Ran Ginosar, Shahar Kvatinsky
2019	J	`jnl`	An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ. IEEE Trans. Very Large Scale Integr. Syst. Ben Perach, Shahar Kvatinsky
2019	J	`jnl`	CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2019	C	`conf`	Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks. ISCAS Loai Danial, Sidharth Thomas, Shahar Kvatinsky
2019	—	`conf`	Logarithmic Neural Network Data Converters using Memristors for Biomedical Applications. BioCAS Loai Danial, Kanishka Sharma, Shivansh Dwivedi, Shahar Kvatinsky
2019	J	`jnl`	MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks. CoRR Tzofnat Greenberg-Toledo, Ben Perach, Daniel Soudry, Shahar Kvatinsky
2019	—	`conf`	Performing Memristor-Aided Logic (MAGIC) using STT-MRAM. ICECS Jeffry Louis, Barak Hoffer, Shahar Kvatinsky
2019	—	`conf`	Real Processing-In-Memory with Memristive Memory Processing Unit. SPACE Shahar Kvatinsky
2019	—	`conf`	Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU). ASAP Shahar Kvatinsky
2019	A	`conf`	STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ. DATE Ben Perach, Shahar Kvatinsky
2019	J	`jnl`	Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse. IEEE Trans. Circuits Syst. I Regul. Pap. Tzofnat Greenberg-Toledo, Roee Mazor, Ameer Haj Ali, Shahar Kvatinsky
2019	J	`jnl`	The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. CoRR Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, Shahar Kvatinsky
2019	C	`conf`	The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors. IOLTS Marco Ottavi, Vishal Gupta, Saurabh Khandelwal, Shahar Kvatinsky, Jimson Mathew, Eugenio Martinelli, Abusaleh M. Jabir
2019	J	`jnl`	Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic. Microelectron. J. Nimrod Wald, Shahar Kvatinsky
2018	J	`jnl`	Analysis of the row grounding technique in a memristor-based crossbar array. Int. J. Circuit Theory Appl. Alexander Dozortsev, Israel Goldshtein, Shahar Kvatinsky
2018	J	`jnl`	Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture. IEEE Trans. Emerg. Top. Comput. Intell. Loai Danial, Nicolás Wainstein, Shraga Kraus, Shahar Kvatinsky
2018	J	`jnl`	DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors. IEEE J. Emerg. Sel. Topics Circuits Syst. Loai Danial, Nicolás Wainstein, Shraga Kraus, Shahar Kvatinsky
2018	C	`conf`	Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC. ISCAS Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Shahar Kvatinsky
2018	J	`jnl`	IMAGING: In-Memory AlGorithms for Image processiNG. IEEE Trans. Circuits Syst. I Regul. Pap. Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
2018	J	`jnl`	Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. IEEE Micro Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
2018	A	`conf`	Practical challenges in delivering the promises of real processing-in-memory machines. DATE Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2018	—	`conf`	Real-Time Trainable Data Converters for General Purpose Applications. NANOARCH Loai Danial, Shahar Kvatinsky
2018	J	`jnl`	TIME - Tunable Inductors Using MEmristors. IEEE Trans. Circuits Syst. I Regul. Pap. Nicolás Wainstein, Shahar Kvatinsky
2017	C	`conf`	An RF memristor model and memristive single-pole double-throw switches. ISCAS Nicolás Wainstein, Shahar Kvatinsky
2017	J	`jnl`	Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. IEEE Des. Test Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky
2017	—	`conf`	Memristive logic: A framework for evaluation and comparison. PATMOS John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2017	A	`conf`	Memristor for computing: Myth or reality? DATE Said Hamdioui, Shahar Kvatinsky, Gert Cauwenberghs, Lei Xie, Nimrod Wald, Siddharth Joshi, Hesham Mostafa Elsayed, Henk Corporaal, Koen Bertels
2017	—	`conf`	Modeling biochemical reactions and gene networks with memristors. BioCAS Hanna Abo Hanna, Loai Danial, Shahar Kvatinsky, Ramez Daniel
2017	C	`conf`	Rate-compatible and high-throughput architecture designs for encoding LDPC codes. ISCAS Nishil Talati, Zhiying Wang, Shahar Kvatinsky
2017	A	`conf`	Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic. ICCAD Rotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky
2017	—	`conf`	Towards a memristive hardware secure hash function (MemHash). HOST Leonid Azriel, Shahar Kvatinsky
2016	J	`jnl`	A Systematic Approach to Blocking Convolutional Neural Networks. CoRR Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz
2016	C	`conf`	A fully analog memristor-based neural network with online gradient training. ISCAS Eyal Rosenthal, Sergey Greshnikov, Daniel Soudry, Shahar Kvatinsky
2016	J	`jnl`	Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. CoRR Ardavan Pedram, Stephen Richardson, Sameh Galal, Shahar Kvatinsky, Mark Horowitz
2016	A*	`conf`	Evaluating programmable architectures for imaging and vision applications. MICRO Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz
2016	A*	`conf`	Improving energy efficiency of DRAM by exploiting half page row access. MICRO Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz
2016	J	`jnl`	Information-Theoretic Sneak-Path Mitigation in Memristor Crossbar Arrays. IEEE Trans. Inf. Theory Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi
2016	C	`conf`	Logic design with unipolar memristors. VLSI-SoC Elad Amrani, Avishay Drori, Shahar Kvatinsky
2016	—	`conf`	Logic with Unipolar Memristors - Circuits and Design Methodology. VLSI-SoC (Selected Papers) Nimrod Wald, Elad Amrani, Avishay Drori, Shahar Kvatinsky
2016	—	`conf`	Memory Processing Unit for in-memory processing. NANOARCH Rotem Ben Hur, Shahar Kvatinsky
2016	J	`jnl`	Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar
2016	B	`conf`	Write sneak-path constraints avoiding disturbs in memristor crossbar arrays. ISIT Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi
2015	J	`jnl`	Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training. IEEE Trans. Neural Networks Learn. Syst. Daniel Soudry, Dotan Di Castro, Asaf Gal, Avinoam Kolodny, Shahar Kvatinsky
2015	J	`jnl`	Multistate Register Based on Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny
2015	J	`jnl`	Resistive Associative Processor. IEEE Comput. Archit. Lett. Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar
2015	J	`jnl`	VTEAM: A General Model for Voltage-Controlled Memristors. IEEE Trans. Circuits Syst. II Express Briefs Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny
2014	J	`jnl`	Logic operations in memory using a memristive Akers array. Microelectron. J. Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky
2014	J	`jnl`	MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014	J	`jnl`	Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014	J	`jnl`	Memristor-Based Multithreading. IEEE Comput. Archit. Lett. Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2013	B	`conf`	Sneak-path constraints in memristor crossbar arrays. ISIT Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi
2013	J	`jnl`	TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2011	C	`conf`	Memristor-based IMPLY logic design procedure. ICCD Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman