Shah M. Jahinuzzaman

11 papers C 1Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2015 — conf
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets.
IRPS
Norbert Seifert, Shah M. Jahinuzzaman, Jyothi Velamala, Nikunj Patel
2012 J jnl
A read-decoupled gated-ground SRAM architecture for low-power embedded memories.
Integr.
Wasim Hussain, Shah M. Jahinuzzaman
2011 — conf
A 7T SRAM bit-cell for low-power embedded memories.
ACM Great Lakes Symposium on VLSI
Wasim Hussain, Shah M. Jahinuzzaman
2011 J jnl
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Mohammad Sharifkhani, Ehsan Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev
2010 C conf
A scalable offset-cancelled current/voltage sense amplifier.
ISCAS
Hourieh Attarzadeh, Mohammad Sharifkhani, Shah M. Jahinuzzaman
2009 J jnl
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
2009 J jnl
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC.
IEEE J. Solid State Circuits
Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev
2008 — conf
A multiword based high speed ECC scheme for low-voltage embedded SRAMS.
ESSCIRC
Shah M. Jahinuzzaman, Tahseen Shakir, Sumanjit Lubana, Jaspal Singh Shah, Manoj Sachdev
2008 — conf
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.
ISQED
Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
2007 — conf
Dynamic Data Stability in Low-power SRAM Design.
CICC
Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
2006 — conf
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.
MTDT
Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev