Shabbir H. Batterywala

17 papers A* 1A 1Misc 12Unranked 3
YearRankTypeTitle / Venue / Authors
2015 Misc conf
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids.
VLSID
Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala
2014 — conf
Fixing Double Patterning violations with look-ahead.
ASP-DAC
Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala
2013 A* conf
Automatic design rule correction in presence of multiple grids and track patterns.
DAC
Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala
2009 Misc conf
Efficient Analog/RF Layout Closure with Compaction Based Legalization.
VLSI Design
Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala
2008 — conf
Cell Swapping Based Migration Methodology for Analog and Custom Layouts.
ISQED
Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
2008 — conf
On Efficient and Robust Constraint Generation for Practical Layout Legalization.
ISQED
Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
2007 Misc conf
A 3-dimensional FEM Based Resistance Extraction.
VLSI Design
Subramanian Rajagopalan, Shabbir H. Batterywala
2007 Misc conf
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.
VLSI Design
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
2006 Misc conf
A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills.
VLSI Design
Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure
2006 Misc conf
MoM - A Process Variation Aware Statistical Capacitance Extractor.
VLSI Design
Rohit Ananthakrishna, Shabbir H. Batterywala
2005 Misc conf
Variance Reduction in Monte Carlo Capacitance Extraction.
VLSI Design
Shabbir H. Batterywala, Madhav P. Desai
2004 Misc conf
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables.
VLSI Design
Shabbir H. Batterywala, Narendra V. Shenoy
2003 Misc conf
A Method to Estimate Slew and Delay in Coupled Digital Circuits.
VLSI Design
Shabbir H. Batterywala, Narendra V. Shenoy
2002 A conf
Track assignment: a desirable intermediate step between global routing and detailed routing.
ICCAD
Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
2001 Misc conf
Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports.
VLSI Design
Shabbir H. Batterywala, H. Narayanan
1999 Misc conf
Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks.
VLSI Design
Shabbir H. Batterywala, H. Narayanan
1997 Misc conf
A New Partitioning Strategy Based on Supermodular Functions.
VLSI Design
Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan