Seyed Mohammad Ali Zeinolabedin

24 papers A 1C 2Journal 9Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications.
IEEE Open J. Circuits Syst.
Amirhossein Rostami, Seyed Mohammad Ali Zeinolabedin, Liyuan Guo, Florian Kelber, Heiner Bauer, Andreas Dixius, Stefan Scholze, Marc Berthel, Dennis Walter, Johannes Uhlig, Bernhard Vogginger, Christian Mayr
2024 — conf
Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants.
MWSCAS
Seyed Mohammad Ali Zeinolabedin, Matthieu Couriol, Pierre-Emmanuel Gaillardon
2023 — conf
A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI.
NEWCAS
Liyuan Guo, Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Annika Weiße, Stefan Scholze, Richard George, Johannes Partzsch, Christian Mayr
2023 — conf
A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI.
NEWCAS
Franz Marcus Schüffny, Stefan Hänzsche, Stephan Henker, Seyed Mohammad Ali Zeinolabedin, Stefan Scholze, Sebastian Höppner, Richard Miru George, Christian Mayr
2023 — conf
A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI.
AICAS
Liyuan Guo, Matthias Jobst, Johannes Partzsch, Stefan Scholze, Andreas Dixius, Matthias Lohrmann, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
2022 J jnl
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.
IEEE Trans. Biomed. Circuits Syst.
Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Richard George, Florian Kelber, Heiner Bauer, Stefan Scholze, Stefan Hänzsche, Marco Stolba, Andreas Dixius, Georg Ellguth, Dennis Walter, Sebastian Höppner, Christian Mayr
2022 — conf
A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm.
NorCAS
Franz Marcus Schüffny, Stefan Hänzsche, Marc Berthel, Seyed Mohammad Ali Zeinolabedin, Stefan Scholze, Sebastian Höppner, Richard Miru George, Christian Mayr
2022 J jnl
An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Franz Marcus Schüffny, Sebastian Höppner, Stefan Hänzsche, Richard Miru George, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
2022 — conf
How to design an input stage for neural recording system in 22 nm FDSOI.
PRIME
Franz Marcus Schüffny, Sebastian Höppner, Seyed Mohammad Ali Zeinolabedin, Richard Miru George, Christian Mayr
2022 — conf
Various Distance Metrics Evaluation on Neural Spike Classification.
BioCAS
Shengpeng Guo, Liyuan Guo, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
2021 A conf
Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator.
DATE
Seyed Mohammad Ali Zeinolabedin, Johannes Partzsch, Christian Mayr
2021 J jnl
Real-time Hardware Implementation of ARM CoreSight Trace Decoder.
IEEE Des. Test
Seyed Mohammad Ali Zeinolabedin, Johannes Partzsch, Christian Mayr
2021 — conf
Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression.
BioCAS
Qier Ma, Liyuan Guo, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
2020 J jnl
Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding.
IEEE Trans. Circuits Syst. II Express Briefs
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
2019 J jnl
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
2016 — conf
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications.
A-SSCC
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
2016 — conf
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm
VLSI Circuits
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
2016 J jnl
A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Tony Tae-Hyoung Kim
2016 — conf
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm
APCCAS
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
2016 J jnl
Structuring of Contourlet Transform for Pipeline-Based Implementation.
Circuits Syst. Signal Process.
Seyed Mohammad Ali Zeinolabedin, Nader Karimi, Shadrokh Samavi, Tony Tae-Hyoung Kim
2015 — conf
A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression.
ESSCIRC
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony T. Kim
2015 J jnl
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony Tae-Hyoung Kim
2015 C conf
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits.
ISCAS
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2014 C conf
An area- and power-efficient FIFO with error-reduced data compression for image/video processing.
ISCAS
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony T. Kim