Seyed Ebrahim Esmaeili

12 papers Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2014 — conf
10 GHz throughput FinFET dual-edge triggered flip-flops.
CCECE
Seyed Ebrahim Esmaeili, Asim J. Al-Khalili
2013 J jnl
Integrated Power and Clock Distribution Network.
IEEE Trans. Very Large Scale Integr. Syst.
Seyed Ebrahim Esmaeili, Asim J. Al-Khalili
2012 — conf
Clock tree structure with reduced wire length using the matched-delay skew compensation technique.
CCECE
Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan
2012 — conf
Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity.
ICECS
Seyed Ebrahim Esmaeili, Riadul Islam, Asim J. Al-Khalili, Glenn E. R. Cowan
2012 J jnl
Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan
2011 — conf
A high performance clock precharge SEU hardened flip-flop.
ASICON
Riadul Islam, Seyed Ebrahim Esmaeili, Thouhidul Islam
2010 J jnl
Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks.
IET Comput. Digit. Tech.
Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan
2010 — conf
Estimating required driver strength in the resonant clock generator.
APCCAS
Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan
2010 J jnl
Skew compensation in energy recovery clock distribution networks.
IET Comput. Digit. Tech.
Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan
2009 — conf
Dual-edge triggered energy recovery DCCER flip-flop for low energy applications.
ECCTD
Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan
2007 — conf
Efficiency Of Components' Region-Constrained Placement To Reduce FPGA's Dynamic Power Consumption.
ICECS
Seyed Ebrahim Esmaeili, Nabil I. Khachab
2006 — conf
Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption.
ISVLSI
Seyed Ebrahim Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam