Sewook Hwang

26 papers C 1Journal 18Unranked 7
YearRankTypeTitle / Venue / Authors
2024 J jnl
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst.
Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song
2021 — conf
34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound.
ISSCC
Nevada Sanchez, Kailiang Chen, Chao Chen, Dan McMahill, Sewook Hwang, Joseph Lutsky, Jungwook Yang, Liewei Bao, Leung Kin Chiu, Graham Peyton, Hamid Soleimani, Bob Ryan, J. R. Petrus, Youn-Jae Kook, Tyler S. Ralston, Keith Fife, Jonathan Rothberg
2021 J jnl
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.
IEEE Access
Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim
2021 J jnl
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Junyoung Song, Sewook Hwang, Chulwoo Kim
2019 J jnl
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits
Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim
2019 J jnl
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs
Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
2018 J jnl
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
2017 — conf
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
ISSCC
Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim
2017 J jnl
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
2017 J jnl
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim
2017 J jnl
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs
Jayoung Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, Chulwoo Kim
2016 — conf
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE.
VLSI Circuits
Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim
2016 J jnl
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.
IEEE Trans. Very Large Scale Integr. Syst.
Junyoung Song, Sewook Hwang, Chulwoo Kim
2016 J jnl
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers.
IEEE Trans. Very Large Scale Integr. Syst.
Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim
2015 — conf
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces.
ISSCC
Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim
2014 J jnl
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
2014 J jnl
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator.
IEEE Trans. Very Large Scale Integr. Syst.
Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim
2013 J jnl
A 0.008 mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Sewook Hwang, Jabeom Koo, Kisoo Kim, Hokyu Lee, Chulwoo Kim
2013 J jnl
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim
2013 J jnl
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Young-Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim
2013 — conf
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process.
ASP-DAC
Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim
2013 J jnl
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor.
IEEE Trans. Very Large Scale Integr. Syst.
Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim
2013 — conf
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
ISSCC
Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim
2012 J jnl
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.
IEEE J. Solid State Circuits
Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2012 C conf
A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS.
ISCAS
Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim
2011 — conf
A 0.076mm
ISSCC
Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim