Seungwhun Paik

22 papers A* 2A 5Journal 10Unranked 5
YearRankTypeTitle / Venue / Authors
2016 J jnl
Wakeup scheduling and its buffered tree synthesis for power gating circuits.
Integr.
Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin
2014 J jnl
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik
2012 J jnl
Clock Gating Synthesis of Pulsed-Latch Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin
2012 J jnl
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin
2011 A conf
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.
ICCAD
Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin
2011 J jnl
Pulsed-Latch Circuits: A New Dimension in ASIC Design.
IEEE Des. Test Comput.
Youngsoo Shin, Seungwhun Paik
2011 — conf
Pulser gating: A clock gating of pulsed-latch circuits.
ASP-DAC
Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin
2011 J jnl
Retiming Pulsed-Latch Circuits With Regulating Pulse Width.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seungwhun Paik, Seonggwan Lee, Youngsoo Shin
2011 J jnl
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks.
J. Circuits Syst. Comput.
Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin
2011 — conf
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance.
ASP-DAC
Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin
2010 — conf
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design.
ASP-DAC
Jun Seomun, Seungwhun Paik, Youngsoo Shin
2010 J jnl
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin
2010 J jnl
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hyein Lee, Seungwhun Paik, Youngsoo Shin
2010 — conf
Statistical time borrowing for pulsed-latch circuit designs.
ASP-DAC
Seungwhun Paik, Lee-eun Yu, Youngsoo Shin
2010 A conf
Wakeup synthesis and its buffered tree construction for power gating circuit designs.
ISLPED
Seungwhun Paik, Sangmin Kim, Youngsoo Shin
2009 A conf
HLS-l: High-level synthesis of high performance latch-based circuits.
DATE
Seungwhun Paik, Insup Shin, Youngsoo Shin
2009 A* conf
Register allocation for high-level synthesis using dual supply voltages.
DAC
Insup Shin, Seungwhun Paik, Youngsoo Shin
2009 A conf
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits.
ICCAD
Seonggwan Lee, Seungwhun Paik, Youngsoo Shin
2009 J jnl
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim
2008 A* conf
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.
DAC
Seungwhun Paik, Youngsoo Shin
2008 A conf
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.
ICCAD
Hyein Lee, Seungwhun Paik, Youngsoo Shin
2008 — conf
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.
ASP-DAC
Jinseob Jeong, Seungwhun Paik, Youngsoo Shin