Seunghwan Lee

12 papers Journal 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
Machine Learning-Driven Extraction of Hybrid Compact Models Integrating Neural Networks and Berkeley Short-Channel Insulated-Gate Field-Effect Transistor Model-Common Multigate for Multidevice Applications.
Adv. Intell. Syst.
Seungjoon Eom, Seunghwan Lee, Hyeok Yun, Kyeongrae Cho, Soomin Kim, Rock-Hyun Baek
2025 J jnl
Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width.
IEEE Access
Sanguk Lee, Jinsu Jeong, Jongseo Park, Seunghwan Lee, Junjong Lee, Yonghwan Ahn, Minchan Kim, Rock-Hyun Baek
2024 J jnl
Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations.
IEEE Access
Seunghwan Lee, Seungjoon Eom, Jinsu Jeong, Junjong Lee, Sanguk Lee, Hyeok Yun, Yonghwan Ahn, Rock-Hyun Baek
2024 J jnl
Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation.
Adv. Intell. Syst.
Seungjoon Eom, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, Rock-Hyun Baek
2024 J jnl
Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring.
Adv. Intell. Syst.
Hyeok Yun, Hyundong Jang, Seunghwan Lee, Junjong Lee, Kyeongrae Cho, Seungjoon Eom, Soomin Kim, Choong-Ki Kim, Hong-Chul Byun, Seongjoo Han, Min-Soo Yoo, Rock-Hyun Baek
2022 J jnl
DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors.
IEEE Access
Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Junjong Lee, Sanguk Lee, Jaewan Lim, Rock-Hyun Baek
2021 J jnl
Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning.
IEEE Access
Jun-Sik Yoon, Seunghwan Lee, Hyeok Yun, Rock-Hyun Baek
2021 J jnl
Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes.
IEEE Access
Junjong Lee, Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Sanguk Lee, Rock-Hyun Baek
2020 J jnl
Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application.
IEEE Access
Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Rock-Hyun Baek
2019 J jnl
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node.
IEEE Access
Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek
2019 J jnl
Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain.
IEEE Access
Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek
2019 J jnl
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node.
IEEE Access
Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jinsu Jeong, Hyeok Yun, Bohyeon Kang, Rock-Hyun Baek