Seung Chul Song

11 papers Journal 7Unranked 4

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time. IEEE J. Solid State Circuits Hanwool Jeong, Juhyun Park, Seung Chul Song, Seong-Ook Jung
2018	J	`jnl`	Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation. IEEE Trans. Very Large Scale Integr. Syst. Hanwool Jeong, Tae Woo Oh, Seung Chul Song, Seong-Ook Jung
2017	—	`conf`	PPAC scaling enablement for 5nm mobile SoC technology. ESSDERC Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta, David Kohen, Po-Wen Chan, Keagan Chen, P. R. Chidi Chidambaram
2016	J	`jnl`	Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2016	—	`conf`	Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. VLSI Circuits Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap
2015	—	`conf`	Holistic technology optimization and key enablers for 7nm mobile SoC. VLSIC Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap
2015	J	`jnl`	SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2015	J	`jnl`	Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2015	—	`conf`	Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization. VLSIC N. N. Mojumder, Seung Chul Song, K. Rim, J. Xu, Joseph Wang, J. Zhu, Milena Vratonjic, K. Lin, Martin Saint-Laurent, Paul Bassett, Geoffrey Yeap
2014	J	`jnl`	Improved device variability in scaled MOSFETs with deeply retrograde channel profile. Microelectron. Reliab. Jason Woo, Po-Yen Chien, Frank Yang, Seung Chul Song, P. R. Chidi Chidambaram, Joseph Wang, Geoffrey Yeap
2011	J	`jnl`	FinFET based SRAM bitcell design for 32 nm node and below. Microelectron. J. Seung Chul Song, M. Abu-Rahma, Geoffrey Yeap