Seung-Tak Ryu - RankMe

99 papers C 2Journal 58Unranked 39

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 12-Bit 600-MS/s Pipelined ADC With Two-Stage High-Gain Dynamic Amplifier in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Bo Gao, Raymond Mabilangan, Chang-Un Park, Kent Edrian Lozada, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
2026	J	`jnl`	A SAR-Assisted Continuous-Time M-0 MASH Delta-Sigma Modulator With Digital-Domain Noise Leakage Shaping. IEEE Open J. Circuits Syst. Kent Edrian Lozada, Bo Gao, Raymond Mabilangan, Charlie Tahar, Kun-Woo Park, Young-Hun Moon, Kwan-Hoon Song, Seung-Tak Ryu
2025	J	`jnl`	A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS. IEEE J. Solid State Circuits Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
2025	—	`conf`	Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling. CICC Kent Edrian Lozada, Il-Hoon Jang, Ye-Dam Kim, Seung-Tak Ryu
2025	J	`jnl`	Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Ippei Akita, Kousuke Miyaji, Seung-Tak Ryu, Masoud Babaie, Negar Reiskarimian
2024	—	`conf`	A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3 VLSI Technology and Circuits Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
2024	J	`jnl`	A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. IEEE J. Solid State Circuits Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu
2024	—	`conf`	A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. VLSI Technology and Circuits Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Chang-Un Park, Kun-Woo Park, Kwan-Hoon Song, Young-Hun Moon, Min-Jae Seo, Seung-Tak Ryu
2024	J	`jnl`	A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. IEEE J. Solid State Circuits Dong-Hun Lee, Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
2024	—	`conf`	A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. A-SSCC Bo Gao, Lizhen Zhang, Raymond Mabilangan, Chang-Un Park, Kent Edrian Lozada, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
2024	—	`conf`	A 5× OSR 1MHz-BW 81dB-SNDR 5 A-SSCC Lizhen Zhang, Bo Gao, Kun-Woo Park, Hyeongjin Kim, Kent Edrian Lozada, Ye-Dam Kim, Jianhui Wu, Seung-Tak Ryu
2024	J	`jnl`	An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver. IEEE Trans. Circuits Syst. II Express Briefs Ji-Wook Kwon, Dong-Hwan Jin, Min-Jae Seo, Seung-Tak Ryu
2024	J	`jnl`	DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation. IEEE Open J. Circuits Syst. Lizhen Zhang, Bo Gao, Kun-Woo Park, Kent Edrian Lozada, Raymond Mabilangan, Hyeongjin Kim, Jianhui Wu, Seung-Tak Ryu
2024	—	`conf`	TID-Tolerant StrongARM Comparator and Sampling Network for Satellite Application High-Voltage ADCs. A-SSCC Charlie Tahar, Changyeop Lee, Kun-Woo Park, Kent Edrian Lozada, Hyojun Kim, Ki-Ho Kwon, Seung-Tak Ryu
2023	—	`conf`	A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration. CICC Chang-Un Park, Jae-Hyun Chung, Seung-Tak Ryu
2023	—	`conf`	A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3 A-SSCC Kent Edrian Lozada, Dong-Hun Lee, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
2023	—	`conf`	An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. CICC Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Min-Jae Seo, Seung-Tak Ryu
2022	J	`jnl`	A 4 IEEE Trans. Circuits Syst. II Express Briefs Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, Seung-Tak Ryu
2022	J	`jnl`	A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique. IEEE J. Solid State Circuits Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu
2022	—	`conf`	A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs. VLSI Technology and Circuits Dong-Jin Chang, Seung-Tak Ryu
2021	J	`jnl`	A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration. IEEE J. Solid State Circuits Dong-Jin Chang, Michael Choi, Seung-Tak Ryu
2021	—	`conf`	A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. A-SSCC Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, Seung-Tak Ryu
2021	J	`jnl`	An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. IEEE J. Solid State Circuits Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, Seung-Tak Ryu
2021	—	`conf`	An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. A-SSCC Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, Seung-Tak Ryu
2021	J	`jnl`	MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs. IEEE Access Dong-Jin Chang, Byeong-Gyu Nam, Seung-Tak Ryu
2020	—	`conf`	A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section. EMBC Jongpal Kim, Wonseok Lee, Junyeub Suh, Hyungwoo Lee, Kyu-Il Lee, Ho Young Ahn, Min-Jae Seo, Seung-Tak Ryu, Kirill Y. Aristovich, David S. Holder, Sang Joon Kim
2020	J	`jnl`	A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC. IEEE Trans. Circuits Syst. Kyoung-Jun Moon, Dong-Ryeol Oh, Michael Choi, Seung-Tak Ryu
2020	J	`jnl`	A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision. IEEE Trans. Circuits Syst. Yi-Ju Roh, Dong-Jin Chang, Seung-Tak Ryu
2020	J	`jnl`	A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. IEEE Trans. Circuits Syst. II Express Briefs Dong-Shin Jo, Ba-Ro-Saim Sung, Min-Jae Seo, Woo-Cheol Kim, Seung-Tak Ryu
2020	J	`jnl`	A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. IEEE J. Solid State Circuits Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Seung-Tak Ryu
2020	—	`conf`	An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. VLSI Circuits Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, Seung-Tak Ryu
2020	J	`jnl`	Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron. IEEE Trans. Circuits Syst. Dong-Jin Chang, Byeong-Gyu Nam, Seung-Tak Ryu
2019	—	`conf`	A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. VLSI Circuits Min-Jae Seo, Ye-Dam Kim, Jae-Hyun Chung, Seung-Tak Ryu
2019	J	`jnl`	A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. IEEE J. Solid State Circuits Dong-Ryeol Oh, Jong-In Kim, Dong-Shin Jo, Woo-Chul Kim, Dong-Jin Chang, Seung-Tak Ryu
2019	—	`conf`	A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. VLSI Circuits Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, Seung-Tak Ryu
2019	J	`jnl`	A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. IEEE J. Solid State Circuits Kyoung-Jun Moon, Dong-Shin Jo, Wan Kim, Michael Choi, Hyungjong Ko, Seung-Tak Ryu
2019	J	`jnl`	A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. IEEE J. Solid State Circuits Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo, Mi-Young Kim, Min-Chul Shin, Seokjoon Kang, Junghyuk Yoon, Taek-Seung Kim, Seung-Tak Ryu
2019	—	`conf`	A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. A-SSCC Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, Seung-Tak Ryu
2019	J	`jnl`	Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC. IET Circuits Devices Syst. Chang-Kyo Lee, Seung-Tak Ryu
2018	J	`jnl`	A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim, Seung-Tak Ryu
2018	J	`jnl`	A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. IEEE J. Solid State Circuits Il-Hoon Jang, Min-Jae Seo, Sang-Hyun Cho, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, Hyungjong Ko, Seung-Tak Ryu
2018	J	`jnl`	A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. IEEE Trans. Circuits Syst. II Express Briefs Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu
2018	J	`jnl`	A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs. IEEE Trans. Circuits Syst. II Express Briefs Si-Nai Kim, Woo-Cheol Kim, Min-Jae Seo, Seung-Tak Ryu
2018	J	`jnl`	A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE Trans. Circuits Syst. II Express Briefs Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim, Seung-Tak Ryu
2018	J	`jnl`	A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme. IEEE J. Solid State Circuits Hyun-Wook Kang, Hyeok-Ki Hong, Wan Kim, Seung-Tak Ryu
2018	J	`jnl`	Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Tsung-Hsien Lin, Chia-Hsiang Yang, Seung-Tak Ryu
2018	—	`conf`	Session 14 overview: High-resolution ADCs: Data converter subcommittee. ISSCC Matt Straayer, Seung-Tak Ryu, Un-Ku Moon
2017	J	`jnl`	A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction. IEEE J. Solid State Circuits Hyeon-June Kim, Sun-Il Hwang, Jae-Hyun Chung, Jong-Ho Park, Seung-Tak Ryu
2017	—	`conf`	An incremental zoom sturdy MASH ADC. MWSCAS Ki-Hoon Seo, Il-Hoon Jang, Kyung-Jun Noh, Seung-Tak Ryu
2017	—	`conf`	F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. ISSCC Kostas Doris, David Robertson, Seung-Tak Ryu, Seng-Pan U
2017	J	`jnl`	Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Tim Piessens, Seung-Tak Ryu, Chih-Ming Hung, Alyosha C. Molnar, Mounir Meghelli
2017	J	`jnl`	Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Dong-Jin Chang, Wan Kim, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu
2016	J	`jnl`	A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. IEEE J. Solid State Circuits Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, Seung-Tak Ryu
2016	C	`conf`	A 54-μW fast-settling arterial pulse wave sensor for wrist watch type system. ISCAS Kwantae Kim, Minseo Kim, Hyunwoo Cho, Kwonjoon Lee, Seung-Tak Ryu, Hoi-Jun Yoo
2016	J	`jnl`	A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs. IEEE J. Solid State Circuits Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu
2016	J	`jnl`	A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm IEEE Trans. Very Large Scale Integr. Syst. Si-Nai Kim, Mee-Ran Kim, Ba-Ro-Saim Sung, Hyun-Wook Kang, Min-Hyung Cho, Seung-Tak Ryu
2016	J	`jnl`	A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. II Express Briefs Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu
2016	—	`conf`	F2: Data-converter calibration and dynamic-matching techniques. ISSCC Kostas Doris, Alyosha C. Molnar, Xicheng Jiang, Seung-Tak Ryu
2015	—	`conf`	26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. ISSCC Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu
2015	—	`conf`	26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. ISSCC Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu
2015	J	`jnl`	A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. IEEE J. Solid State Circuits Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Junho Cheon, Seung-Tak Ryu
2015	—	`conf`	A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. ESSCIRC Dong-Ryeol Oh, Jong-In Kim, Min-Jae Seo, Jin-Gwang Kim, Seung-Tak Ryu
2015	J	`jnl`	A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. IEEE J. Solid State Circuits Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung, Seung-Tak Ryu
2015	J	`jnl`	A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. IEEE J. Solid State Circuits Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu
2015	—	`conf`	Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. A-SSCC Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu
2015	—	`conf`	Session 15 overview: Data-converter techniques: Data converters subcommittee. ISSCC Seung-Tak Ryu, Matt Straayer
2015	J	`jnl`	Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs. IEICE Electron. Express Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu
2014	—	`conf`	23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface. ISSCC Young-sub Yuk, Seungchul Jung, Hui-Dong Gwon, Sukhwan Choi, Si-Duk Sung, Tae-Hwang Kong, Sung-Wan Hong, Jun-Han Choi, Min-Yong Jeong, Jong-Pil Im, Seung-Tak Ryu, Gyu-Hyeong Cho
2014	J	`jnl`	A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications. IEEE Trans. Circuits Syst. II Express Briefs Ghil-Geun Oh, Chang-Kyo Lee, Seung-Tak Ryu
2014	J	`jnl`	A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs. IEEE J. Solid State Circuits Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho
2014	—	`conf`	A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. CICC Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, Seung-Tak Ryu
2013	—	`conf`	A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs. ISSCC Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho
2013	J	`jnl`	A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. IEEE J. Solid State Circuits Jong-In Kim, Ba-Ro-Saim Sung, Wan Kim, Seung-Tak Ryu
2013	J	`jnl`	A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels. IEEE Trans. Circuits Syst. I Regul. Pap. Junhyeok Yang, Seungchul Jung, Young-Suk Son, Seung-Tak Ryu, Gyu-Hyeong Cho
2013	J	`jnl`	A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design. IEEE Trans. Circuits Syst. II Express Briefs Chang-Kyo Lee, Wan Kim, Hyun-Wook Kang, Seung-Tak Ryu
2013	—	`conf`	A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels. ISSCC Junhyeok Yang, Sang-Hui Park, Jung-Min Choi, Hyunsik Kim, Changbyung Park, Seung-Tak Ryu, Gyu-Hyeong Cho
2013	—	`conf`	An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. ISSCC Hyeok-Ki Hong, Hyun-Wook Kang, Barosaim Sung, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, Seung-Tak Ryu
2013	J	`jnl`	An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers. IEEE Trans. Circuits Syst. II Express Briefs Seung-Yeob Baek, Jae-Kyum Lee, Seung-Tak Ryu
2013	J	`jnl`	An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution. IEEE J. Solid State Circuits Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-Il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho
2012	J	`jnl`	A 180-µW, 120-MHz, Fourth Order Low-Pass Bessel Filter Based on FVF Biquad Structure. IEICE Trans. Electron. Hundo Shin, Seung-Tak Ryu
2012	J	`jnl`	A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting. IEEE J. Solid State Circuits Jong-Pil Im, Se-Won Wang, Seung-Tak Ryu, Gyu-Hyeong Cho
2012	—	`conf`	A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting. ISSCC Jong-Pil Im, Se-Won Wang, Kang-Ho Lee, Young-Jin Woo, Young-sub Yuk, Tae-Hwang Kong, Sung-Wan Hong, Seung-Tak Ryu, Gyu-Hyeong Cho
2012	—	`conf`	A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control. CICC Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu
2012	J	`jnl`	A Single-Supply 84 dB DR Audio-Band ADC for Compact Digital Microphones. IEICE Trans. Electron. Huy-Binh Le, Sang-Gug Lee, Seung-Tak Ryu
2012	J	`jnl`	A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm. IEEE Trans. Very Large Scale Integr. Syst. Sang-Hyun Cho, Chang-Kyo Lee, Sang-Gug Lee, Seung-Tak Ryu
2012	—	`conf`	A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel. ISSCC Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-Il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho
2011	—	`conf`	A 0.014mm ISSCC Hyunsik Kim, Jinyong Jeon, Sungwoo Lee, Junhyeok Yang, Seung-Tak Ryu, Gyu-Hyeong Cho
2011	J	`jnl`	A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction. IEEE J. Solid State Circuits Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu
2011	J	`jnl`	A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers. IEEE Trans. Circuits Syst. II Express Briefs Hyunsik Kim, Jinyong Jeon, Sungwoo Lee, Junhyeok Yang, Seung-Tak Ryu, Gyu-Hyeong Cho
2011	J	`jnl`	A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability. IEEE Trans. Circuits Syst. II Express Briefs Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee, Seung-Tak Ryu
2011	—	`conf`	A time-domain latch interpolation technique for low power flash ADCs. CICC Jong-In Kim, Wan Kim, Barosaim Sung, Seung-Tak Ryu
2010	—	`conf`	A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction. CICC Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu
2010	—	`conf`	A novel readout IC with high noise immunity for charge-based touch screen panels. CICC Junhyeok Yang, Seungchul Jung, Young-Jin Woo, Jinyong Jeon, Sungwoo Lee, Changbyung Park, Hyunsik Kim, Seung-Tak Ryu, Gyu-Hyeong Cho
2010	J	`jnl`	Yield-Ensuring DAC-Embedded Opamp Design Based on Accurate Behavioral Model Development. IEICE Trans. Electron. Yeong-Shin Jang, Hoai-Nam Nguyen, Seung-Tak Ryu, Sang-Gug Lee
2009	J	`jnl`	A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones. IEICE Trans. Electron. Huy-Binh Le, Seung-Tak Ryu, Sang-Gug Lee
2009	C	`conf`	A Time-interleaved Flash-SAR Architecture for High Speed A/D Conversion. ISCAS Ba Sung, Sang-Hyun Cho, Chang-Kyo Lee, Jong-In Kim, Seung-Tak Ryu
2007	J	`jnl`	A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse. IEEE J. Solid State Circuits Seung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania
2006	—	`conf`	A 10b 50MS/s pipelined ADC with opamp current reuse. ISSCC Seung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania
2004	J	`jnl`	A 14-b linear capacitor self-trimming pipelined ADC. IEEE J. Solid State Circuits Seung-Tak Ryu, Sourja Ray, Bang-Sup Song, Gyu-Hyeong Cho, Kantilal Bacrania