Sergio López-Buedo

51 papers A* 1A 4B 9Misc 1Journal 17Unranked 19

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies. IEEE Trans. Circuits Syst. II Express Briefs Tobias Alonso, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara
2022	J	`jnl`	Demonstration of latency-aware 5G network slicing on optical metro networks. CoRR Behnam Shariati, Luis Velasco, Jose-Juan Pedreno-Manresa, Annika Dochhan, Ramon Casellas, Abubakar Siddique Muqaddas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco Javier Moreno, Pablo Pavón, Marc Ruiz, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes K. Fischer, Ronald Freund
2022	J	`jnl`	Demonstration of latency-aware 5G network slicing on optical metro networks. JOCN Behnam Shariati, Luis Velasco, Jose-Juan Pedreno-Manresa, Annika Dochhan, Ramon Casellas, Abubakar Siddique Muqaddas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco-Javier Moreno-Muro, Pablo Pavón, Marc Ruiz, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes K. Fischer, Ronald Freund
2021	—	`conf`	A Latency-Aware Real-Time Video Surveillance Demo: Network Slicing for Improving Public Safety. OFC Behnam Shariati, Jose-Juan Pedreno-Manresa, Annika Dochhan, Abubakar Siddique Muqaddas, Ramon Casellas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco Javier Moreno, Pablo Pavón, Luis Velasco, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes Karl Fischer, Ronald Freund
2021	J	`jnl`	A Latency-Aware Real-Time Video Surveillance Demo: Network Slicing for Improving Public Safety. CoRR Behnam Shariati, Jose-Juan Pedreno-Manresa, Annika Dochhan, Abubakar Siddique Muqaddas, Ramon Casellas, Óscar González de Dios, Lourdes Luque Canto, Bodo Lent, Jorge E. López de Vergara, Sergio López-Buedo, Francisco Javier Moreno, Pablo Pavón, Luis Velasco, Sai Kireet Patri, Alessio Giorgetti, Filippo Cugini, Andrea Sgambelluri, Reza Nejabati, Dimitra Simeonidou, Ralf-Peter Braun, Achim Autenrieth, Jörg-Peter Elbers, Johannes Karl Fischer, Ronald Freund
2019	B	`conf`	Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. FPL Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo
2018	—	`conf`	FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. ReConFig Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso
2018	A*	`conf`	Understanding PCIe performance for end host networking. SIGCOMM Rolf Neugebauer, Gianni Antichi, José Fernando Zazo, Yury Audzevich, Sergio López-Buedo, Andrew W. Moore
2018	A	`conf`	dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter. DATE Maciej Bielski, Ilias Syrigos, Kostas Katrinis, Dimitris Syrivelis, Andrea Reale, Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisis N. Pnevmatikatos, E. H. Pap, George Zervas, Vaibhawa Mishra, Arsalan Saljoghei, Alvise Rigo, Jose Fernando Zazo, Sergio López-Buedo, Martí Torrents, Ferad Zyulkyarov, Michael Enrico, Óscar González de Dios
2017	—	`conf`	A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. ReConFig Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter
2017	—	`conf`	An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. ReConFig Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara
2017	—	`conf`	Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis. HPCC/SmartCity/DSS Carlos Vega, Jose Fernando Zazo, Hugo Meyer, Ferad Zyulkyarov, Sergio López-Buedo, Javier Aracil
2017	J	`jnl`	Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis. CoRR Carlos Vega, Jose Fernando Zazo, Hugo Meyer, Ferad Zyulkyarov, Sergio López-Buedo, Javier Aracil
2016	J	`jnl`	Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks. IEEE Commun. Mag. Mario Ruiz, Javier Ramos, Gustavo Sutter, Jorge E. López de Vergara, Sergio López-Buedo, Javier Aracil
2016	—	`conf`	Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. ReConFig Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil
2016	—	`conf`	FPGA-based encrypted network traffic identification at 100 Gbit/s. ReConFig Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara
2016	B	`conf`	Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. FPL Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna
2016	—	`conf`	On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision. EuCNC Kostas Katrinis, Georgios Zervas, Dionisios N. Pnevmatikatos, Dimitris Syrivelis, Theoni Alexoudi, Dimitris Theodoropoulos, Daniel Raho, Christian Pinto, Felix Espina, Sergio López-Buedo, Qianqiao Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends
2016	A	`conf`	Rack-scale disaggregated cloud data centers: The dReDBox project vision. DATE Kostas Katrinis, Dimitris Syrivelis, Dionisios N. Pnevmatikatos, Georgios Zervas, Dimitris Theodoropoulos, Iordanis Koutsopoulos, K. Hasharoni, Daniel Raho, Christian Pinto, Felix Espina, Sergio López-Buedo, Qianqiao Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends
2015	—	`conf`	A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances. ReConFig Jose Fernando Zazo, Sergio López-Buedo, Yury Audzevich, Andrew W. Moore
2015	—	`conf`	Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. ReConFig Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Javier Ramos, Jorge E. López de Vergara, Javier Aracil
2014	J	`jnl`	Bridging the gap between hardware and software open source network developments. IEEE Netw. Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, Javier Aracil
2014	—	`conf`	TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. ReConFig Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil
2013	B	`conf`	Accurate and flexible flow-based monitoring for high-speed networks. FPL Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Javier Aracil
2013	J	`jnl`	FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. J. Syst. Archit. Diego Sanchez-Roman, Victor Moreno, Sergio López-Buedo, Gustavo Sutter, Iván González, Francisco J. Gomez-Arribas, Javier Aracil
2013	—	`conf`	IDEALIST control and service management solutions for dynamic and adaptive flexi-grid DWDM networks. Future Network & Mobile Summit Raul Muñoz, Víctor López, Ramon Casellas, Óscar González de Dios, Filippo Cugini, Nicola Sambo, Antonio D'Errico, Ori Gerstel, Daniel King, Sergio López-Buedo, Patricia Layec, Antonio Cimmino, Ricardo Martínez, Roberto Morro
2012	J	`jnl`	A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers. Int. J. Reconfigurable Comput. Esam El-Araby, Iván González, Sergio López-Buedo, Tarek A. El-Ghazawi
2012	—	`conf`	A FPGA-based scalable architecture for URL legal filtering in 100GbE networks. ReConFig Jaime J. Garnica, Sergio López-Buedo, Víctor López, Javier Aracil, José María Gómez Hidalgo
2012	J	`jnl`	Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. J. Syst. Archit. Iván González, Sergio López-Buedo, Gustavo Sutter, Diego Sanchez-Roman, Francisco J. Gomez-Arribas, Javier Aracil
2011	J	`jnl`	Characterization of the busy-hour traffic of IP networks based on their intrinsic features. Comput. Networks José Luis García-Dorado, José Alberto Hernández, Javier Aracil, Jorge E. López de Vergara, Sergio López-Buedo
2011	J	`jnl`	High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. IEEE Des. Test Comput. Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Iván González, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios
2011	—	`conf`	High-accuracy network monitoring using ETOMIC testbed. NGI Victor Moreno, Jaime J. Garnica, Francisco J. Gomez-Arribas, Sergio López-Buedo, Iván González, Javier Aracil, Mikel Izal, Eduardo Magaña, Daniel Morató
2008	—	`conf`	A Framework to Improve IP Portability on Reconfigurable Computers. ERSA Miaoqing Huang, Iván González, Sergio López-Buedo, Tarek A. El-Ghazawi
2008	J	`jnl`	Implementation of secure applications in self-reconfigurable systems. Microprocess. Microsystems Iván González, Sergio López-Buedo, Francisco J. Gomez-Arribas
2008	J	`jnl`	Portable library development for reconfigurable computing systems: A case study. Parallel Comput. Proshanta Saha, Esam El-Araby, Miaoqing Huang, Mohamed Taher, Sergio López-Buedo, Tarek A. El-Ghazawi, Chang Shu, Kris Gaj, Alan Michalski, Duncan A. Buell
2007	—	`conf`	A Quality of Service Assessment Technique for Large-Scale Management of Multimedia Flows. MMNS José Luis García-Dorado, Javier Aracil, José Alberto Hernández, Sergio López-Buedo, Jorge E. López de Vergara, Pedro Reviriego, Gabriel Huecas, Santiago Pavón, Juan Quemada
2007	J	`jnl`	Self-Reconfigurable Embedded Systems on Low-Cost FPGAs. IEEE Micro Iván González, Estanislao Aguayo, Sergio López-Buedo
2006	Misc	`conf`	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo
2005	—	`conf`	Hardware-Accelerated SSH on Self-Reconfigurable Systems. FPT Iván González, Francisco J. Gomez-Arribas, Sergio López-Buedo
2004	A	`conf`	Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. FPGA Sergio López-Buedo, Eduardo I. Boemo
2003	B	`conf`	Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm. FPL Iván González, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez
2002	B	`conf`	A Tool for Activity Estimation in FPGAs. FPL Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo
2002	B	`conf`	FSM Decomposition for Low Power in FPGA. FPL Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
2002	—	`conf`	Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
2002	B	`conf`	Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. FPL Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo
2000	—	`conf`	A biologically inspired autonomous robot that learns approach-avoidance behaviors. Agents Luis Fernando Lago-Fernández, Manuel A. Sánchez-Montañés, Sergio López-Buedo
2000	J	`jnl`	Thermal Testing on Reconfigurable Computers. IEEE Des. Test Comput. Sergio López-Buedo, Javier Garrido Salas, Eduardo I. Boemo
1998	J	`jnl`	Some experiments about wave pipelining on FPGA's. IEEE Trans. Very Large Scale Integr. Syst. Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses
1997	B	`conf`	Thermal monitoring on FPGAs using ring-oscillators. FPL Eduardo I. Boemo, Sergio López-Buedo
1996	A	`conf`	The Wave Pipeline Effect on LUT-Based FPGA Architectures. FPGA Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses
1995	B	`conf`	Some Notes on Power Management on FPGA-Based Systems. FPL Eduardo I. Boemo, Guillermo González de Rivera, Sergio López-Buedo, Juan M. Meneses