Sergei Devadze

49 papers A 6B 3C 6Misc 2Journal 12Unranked 20

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Architectural Exploration and Implementation of CERN LHC Trigger Algorithm With FPGA. IEEE Trans. Very Large Scale Integr. Syst. Sergei Devadze, Christine Elizabeth Nielsen, Natalia Cherezova, Dmitri Mihhailov, Peeter Ellervee
2024	—	`conf`	Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. NorCAS Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee
2024	J	`jnl`	Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. CoRR Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee
2024	—	`conf`	Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab
2023	—	`conf`	On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2023	J	`jnl`	On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2022	J	`jnl`	HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. CoRR Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman
2019	C	`conf`	Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran
2018	—	`conf`	Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
2018	—	`conf`	Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
2017	J	`jnl`	Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure. IEEE Des. Test Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken
2017	A	`conf`	Marginal PCB assembly defect detection on DDR3/4 memory bus. ITC Sergei Odintsov, Artur Jutman, Sergei Devadze
2017	J	`jnl`	Run-time reconfigurable instruments for advanced board-level testing. IEEE Instrum. Meas. Mag. Igor Aleksejev, Artur Jutman, Sergei Devadze
2016	A	`conf`	A suite of IEEE 1687 benchmark networks. ITC Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
2016	C	`conf`	Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2016	B	`conf`	On coverage of timing related faults at board level. ETS Artur Jutman, Igor Aleksejev, Sergei Devadze
2016	—	`conf`	On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs. LATS Konstantin Shibin, Sergei Devadze, Artur Jutman
2016	J	`jnl`	Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. J. Electron. Test. Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
2015	C	`conf`	Combinational fault simulation in sequential circuits. ISCAS Raimund Ubar, Jaak Kousaar, Maksim Gorev, Sergei Devadze
2015	A	`conf`	Fault simulation with parallel exact critical path tracing in multiple core environment. DATE Maksim Gorev, Raimund Ubar, Sergei Devadze
2015	J	`jnl`	Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
2015	J	`jnl`	Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
2015	—	`conf`	Virtual reconfigurable scan-chains on FPGAs for optimized board test. LATS Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
2014	—	`conf`	Asynchronous Fault Detection in IEEE P1687 Instrument Network. NATW Konstantin Shibin, Sergei Devadze, Artur Jutman
2014	C	`conf`	Critical Path Tracing Based Simulation of Transition Delay Faults. DSD Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
2014	—	`conf`	Design, Verification, and Application of IEEE 1687. ATS Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath
2013	—	`conf`	At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
2013	J	`jnl`	Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. IEEE Des. Test Artur Jutman, Sergei Devadze, Konstantin Shibin
2013	—	`conf`	On in-system programming of non-volatile memories. MIXDES Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski
2012	B	`conf`	Embedded synthetic instruments for Board-Level testing. ETS Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel
2012	A	`conf`	FPGA-based synthetic instrumentation for board test. ITC Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel
2011	—	`conf`	Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2011	J	`jnl`	Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Comput. Pract. Exp. Eero Ivask, Sergei Devadze, Raimund Ubar
2011	—	`conf`	Invited paper: System-wide fault management based on IEEE P1687 IJTAG. ReCoSoC Artur Jutman, Sergei Devadze, Igor Aleksejev
2011	C	`conf`	SoC and Board Modeling for Processor-Centric Board Testing. DSD Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2010	—	`conf`	Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS Eero Ivask, Sergei Devadze, Raimund Ubar
2010	Misc	`conf`	Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC Eero Ivask, Sergei Devadze, Raimund Ubar
2010	—	`conf`	Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	A	`conf`	Parallel X-fault simulation with critical path tracing technique. DATE Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	C	`conf`	Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	—	`conf`	Testing beyond the SoCs in a lego style. EWDTS Anton Tsertov, Artur Jutman, Sergei Devadze
2009	A	`conf`	Fast extended test access via JTAG and FPGAs. ITC Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2009	—	`conf`	Turning JTAG inside out for fast extended test access. LATW Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2008	—	`conf`	Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee
2008	—	`conf`	Parallel fault backtracing for calculation of fault coverage. ASP-DAC Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2007	J	`jnl`	Learning Digital Test and Diagnostics via Internet. Int. J. Online Eng. Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke
2007	B	`conf`	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ETS Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2006	—	`conf`	Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. LATW Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar
2005	Misc	`conf`	Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman