Serge Weber - RankMe

50 papers A 1B 7C 3Misc 2Journal 11Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	SWAP-GNG: A Scalable HW Architecture for Multi Growing Neural Gas Graph Learning for Continual Learning. AICAS Florent Derue, Slavisa Jovanovic, Hassan Rabah, Serge Weber
2023	J	`jnl`	A Transformer Neural Network For AC series arc-fault detection. Eng. Appl. Artif. Intell. Alexis Chabert, Mohamed Chafik Bakkay, Patrick Schweitzer, Serge Weber, Jonathan Andrea
2022	J	`jnl`	State-Space Simulation of Electric Arc Faults. IEEE Trans. Aerosp. Electron. Syst. Alexis Chabert, Patrick Schweitzer, Serge Weber, Jonathan Andrea
2020	—	`conf`	Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantization. ICECS Slavisa Jovanovic, Hassan Rabah, Serge Weber, Khaled Ben Khalifa, Mohamed Hédi Bedoui
2019	B	`conf`	A Multi-Application, Scalable and Adaptable Hardware SOM Architecture. IJCNN Mehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui
2019	C	`conf`	AC series arc fault detection with stacked autoencoders. IECON Hien Duc Vu, Edwin Calderon, Patrick Schweitzer, Serge Weber, Nicolas Britsch
2018	J	`jnl`	A scalable and adaptable hardware NoC-based self organizing map. Microprocess. Microsystems Mehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui
2018	C	`conf`	High performance scalable hardware SOM architecture for real-time vector quantization. IPAS Slavisa Jovanovic, Hassan Rabah, Serge Weber
2016	—	`conf`	A Scalable Flexible SOM NoC-Based Hardware Architecture. WSOM Mehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui
2016	—	`conf`	A hardware configurable self-organizing map for real-time color quantization. ICECS Mehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hedi Bedoui
2014	J	`jnl`	A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores. IEEE Embed. Syst. Lett. Nicolas Marques, Hassan Rabah, Eric Dabellani, Serge Weber
2013	J	`jnl`	Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM. Microprocess. Microsystems François Duhem, Nicolas Marques, Fabrice Muller, Hassan Rabah, Serge Weber, Philippe Lorenzini
2013	—	`conf`	Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks. AHS Nicolas Marques, Hassan Rabah, Slavisa Jovanovic, Eric Dabellani, Serge Weber
2013	—	`conf`	Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation. ICECS Eric Dabellani, Hassan Rabah, Nicolas Marques, Yves Berviller, Slavisa Jovanovic, Serge Weber
2012	—	`conf`	An approach: FPGA based dynamically reconfigurable architecture to enable several scheme controls for power converters. CCE Eber Espino Garibay, Domingo Torres, Serge Weber
2011	—	`conf`	An efficient VLSI implementation of H.264/AVC intra-frame transcoder. ICECS Michael Guarisco, Eric Dabellani, Nicolas Marques, Hassan Rabah, Yves Berviller, Serge Weber
2011	—	`conf`	Efficient reconfigurable entropy coder for embedded multi-standards video adaptation. CVPR Workshops Nicolas Marques, Hassan Rabah, Eric Dabellani, Serge Weber
2009	B	`conf`	A new deadlock-free fault-tolerant routing algorithm for NoC interconnections. FPL Slavisa Jovanovic, Camel Tanougast, Serge Weber, Christophe Bobda
2009	J	`jnl`	An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis. IEEE Trans. Circuits Syst. Video Technol. Camel Tanougast, Michael Janiaut, Yves Berviller, Hassan Rabah, Serge Weber, Ahmed Bouridane
2009	J	`jnl`	CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs. Microprocess. Microsystems Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber
2009	—	`conf`	FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. SoCC Michael Guarisco, Hassan Rabah, Yves Berviller, Serge Weber, Said Belkouch
2008	—	`conf`	A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems. ARC Slavisa Jovanovic, Camel Tanougast, Serge Weber
2008	—	`conf`	A framework of architectural synthesis for dynamically reconfigurable FPGAs. SoCC Ting Liu, Camel Tanougast, Serge Weber
2008	—	`conf`	A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems. ASAP Slavisa Jovanovic, Camel Tanougast, Serge Weber
2008	—	`conf`	An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip. ISVLSI Xun Zhang, Hassan Rabah, Serge Weber
2008	—	`conf`	Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC. DELTA Xun Zhang, Hassan Rabah, Serge Weber
2008	—	`conf`	VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher. DELTA Camel Tanougast, Serge Weber, Gilles Millerioux, Jamal Daafouz, Ahmed Bouridane
2007	—	`conf`	A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs. ReCoSoC Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber
2007	—	`conf`	A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems. AHS Slavisa Jovanovic, Camel Tanougast, Serge Weber
2007	—	`conf`	An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performance. AHS Camel Tanougast, Serge Weber, Gilles Millerioux, Ahmed Bouridane, Jamal Daafouz
2007	—	`conf`	Auto-adaptive reconfigurable architecture for scalable multimedia applications. AHS Xun Zhang, Hassan Rabah, Serge Weber
2007	—	`conf`	Cluster-Based Hybrid Reconfigurable Architecture for Auto-adaptive SoC. ICECS Xun Zhang, Hassan Rabah, Serge Weber
2007	B	`conf`	CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs. FPL Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber
2007	J	`jnl`	The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation. J. Univers. Comput. Sci. Oscar Pérez, Yves Berviller, Camel Tanougast, Serge Weber
2006	—	`conf`	Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable system. ICECS Ting Liu, Camel Tanougast, Serge Weber
2005	B	`conf`	Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. FPL Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber
2004	B	`conf`	FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. FPL Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
2004	—	`conf`	FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T. ESA/VLSI Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber
2004	C	`conf`	SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation. IEEE International Workshop on Rapid System Prototyping Camel Tanougast, Yves Berviller, Christian Mannino, Hassan Rabah, Michael Janiaut, Serge Weber
2003	J	`jnl`	A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems. EURASIP J. Adv. Signal Process. Camel Tanougast, Yves Berviller, Serge Weber, Philippe Brunet
2003	A	`conf`	Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design. IPDPS Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber
2003	—	`conf`	Hardware Partitioning Software for Dynamically Reconfigurable SoC Design. IWSOC Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber
2003	J	`jnl`	Linear array processors with multiple access modes memory for real-time image processing. Real Time Imaging Hassan Rabah, Hervé Mathias, Serge Weber, Eril Mozef, Camel Tanougast
2003	J	`jnl`	Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. Microprocess. Microsystems Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber, Hassan Rabah
2002	—	`conf`	Linear array processors with multiple access modes memory for real-time image processing. APCCAS (1) Hassan Rabah, Hervé Mathias, Eril Mozef, Domingo Torres, Serge Weber
2002	B	`conf`	SOPC-based Embedded Smart Strain Gage Sensor. FPL Sylvain Poussier, Hassan Rabah, Serge Weber
2000	—	`conf`	Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation. IPDPS Workshops Camel Tanougast, Yves Berviller, Serge Weber
1999	Misc	`conf`	SIMD/restricted MIMD parallel architecture for Image Processing Based on a New Design of a Multi-mode Access Memory. PDPTA Domingo Torres, Hervé Mathias, Hassan Rabah, Serge Weber
1996	Misc	`conf`	LAPCAM, Linear Array of Processors Using Content-Addressable Memories: A New Design of Machine Vision for Parallel Image Computations. MVA Eril Mozef, Serge Weber, Jamal Jaber, Claude Bataille
1996	B	`conf`	Parallel architecture dedicated to connected component analysis. ICPR Eril Mozef, Serge Weber, Jamal Jaber, Etienne Tisserand