Serge Pravossoudovitch

135 papers A* 3A 17B 10C 17Misc 15Journal 29Unranked 44

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
2016	J	`jnl`	A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
2015	—	`conf`	An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
2014	—	`conf`	A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	J	`jnl`	A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2014	J	`jnl`	Intra-Cell Defects Diagnosis. J. Electron. Test. Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
2014	C	`conf`	Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2013	—	`conf`	Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
2013	—	`conf`	On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	C	`conf`	SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	—	`conf`	Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	Misc	`conf`	Advanced test methods for SRAMs. VTS Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	J	`jnl`	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC J. Electron. Test. Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2012	J	`jnl`	Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	B	`conf`	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
2011	—	`conf`	A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2011	C	`conf`	A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch
2011	C	`conf`	On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2011	A	`conf`	On using address scrambling to implement defect tolerance in SRAMs. ITC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	C	`conf`	Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	J	`jnl`	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed
2010	J	`jnl`	A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2010	—	`conf`	A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2010	—	`conf`	A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo
2010	A*	`conf`	A statistical simulation method for reliability analysis of SRAM core-cells. DAC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	B	`conf`	A two-layer SPICE model of the ATMEL TSTAC ETS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2010	—	`conf`	An Exact and Efficient Critical Path Tracing Algorithm. DELTA Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2010	C	`conf`	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen
2010	B	`conf`	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	Misc	`conf`	Detecting NBTI induced failures in SRAM core-cells. VTS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	—	`conf`	Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	A	`conf`	Is test power reduction through X-filling good enough? ITC Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
2010	A	`conf`	Parity prediction synthesis for nano-electronic gate designs. ITC D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2010	B	`conf`	Setting test conditions for improving SRAM reliability. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2009	J	`jnl`	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2009	—	`conf`	A case study on logic diagnosis for System-on-Chip. ISQED Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	A	`conf`	A new design-for-test technique for SRAM core-cell stability faults. DATE Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2009	C	`conf`	An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2009	J	`jnl`	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2009	C	`conf`	Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	—	`conf`	Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2009	J	`jnl`	Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2009	A	`conf`	NAND flash testing: A preliminary study on actual defects. ITC Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard
2008	A	`conf`	A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2008	A	`conf`	A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2008	J	`jnl`	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2008	Misc	`conf`	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2008	—	`conf`	Improving Diagnosis Resolution without Physical Information. DELTA Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	C	`conf`	SoC Symbolic Simulation: a case study on delay fault testing. DDECS Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi
2008	A	`conf`	SoC Yield Improvement: Redundant Architectures to the Rescue? ITC Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	—	`conf`	Using TMR Architectures for Yield Improvement. DFT Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	C	`conf`	Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	C	`conf`	A Mixed Approach for Unified Logic Diagnosis. DDECS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	A concurrent approach for testing address decoder faults in eFlash memories. ITC Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga
2007	J	`jnl`	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	B	`conf`	DERRIC: A Tool for Unified Logic Diagnosis. ETS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	B	`conf`	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	B	`conf`	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Fast Bridging Fault Diagnosis using Logic Information. ATS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel
2007	Misc	`conf`	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	Misc	`conf`	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	J	`jnl`	A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	J	`jnl`	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2006	J	`jnl`	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2006	Misc	`conf`	An Overview of Failure Mechanisms in Embedded Flash Memories. VTS Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	C	`conf`	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	—	`conf`	Power-Aware Test Data Compression for Embedded IP Cores. ATS Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault
2006	C	`conf`	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
2005	J	`jnl`	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2005	—	`conf`	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2005	Misc	`conf`	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	J	`jnl`	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2005	J	`jnl`	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan
2005	B	`conf`	Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	A*	`conf`	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2005	C	`conf`	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
2004	C	`conf`	BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	A	`conf`	Design of Routing-Constrained Low Power Scan Chains. DATE Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	—	`conf`	Design of Routing-Constrained Low Power Scan Chains. DELTA Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	B	`conf`	Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2004	—	`conf`	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	B	`conf`	Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	Misc	`conf`	March iC-: An Improved Version of March C- for ADOFs Detection. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
2004	J	`jnl`	Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2004	—	`conf`	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2003	—	`conf`	Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
2003	C	`conf`	Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2003	—	`conf`	Defect-oriented dynamic fault models for embedded-SRAMs. ETW Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2003	A	`conf`	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2003	—	`conf`	Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2002	J	`jnl`	Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002	J	`jnl`	High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
2002	Misc	`conf`	On Using Efficient Test Sequences for BIST. VTS René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002	A	`conf`	Power Driven Chaining of Flip-Flops in Scan Architectures. ITC Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2002	—	`conf`	Test Power: a Big Issue in Large SOC Designs. DELTA Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	Misc	`conf`	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2001	J	`jnl`	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	On hardware generation of random single input change test sequences. ETW René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2001	C	`conf`	Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2000	—	`conf`	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	Delay fault testing: choosing between random SIC and random MIC test sequences. ETW Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2000	J	`jnl`	Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
2000	A	`conf`	Low power BIST design by hypergraph partitioning: methodology and architectures. ITC Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
1999	J	`jnl`	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
1999	Misc	`conf`	A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	Low power BIST by filtering non-detecting vectors. ETW Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
1998	—	`conf`	A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
1997	A	`conf`	A gate resizing technique for high reduction in power consumption. ISLPED Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
1997	J	`jnl`	A non-iterative gate resizing algorithm for high reduction in power consumption. Integr. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
1997	Misc	`conf`	An optimized BIST test pattern generator for delay testing. VTS Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch
1996	A	`conf`	A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1996	Misc	`conf`	A new test pattern generation method for delay fault testing. VTS S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1996	—	`conf`	DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ED&TC P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1995	—	`conf`	A trace-based method for delay fault diagnosis in synchronous sequential circuits. ED&TC Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1995	J	`jnl`	An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Test. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1995	J	`jnl`	Delay fault diagnosis in sequential circuits based on path tracing. Integr. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1995	Misc	`conf`	Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1994	—	`conf`	Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1993	A	`conf`	An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	Misc	`conf`	A New Reliable Method for Delay-Fault Diagnosis. VLSI Design Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	A*	`conf`	A Novel Approach to Delay-Fault Diagnosis. DAC Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	J	`jnl`	Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Des. Test Comput. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1991	J	`jnl`	Fault modeling and fault equivalence in CMOS technology. J. Electron. Test. Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch
1990	—	`conf`	Fault modelling and fault equivalence in CMOS technology. EURO-DAC Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch