Seoyoung Jang

13 papers C 2Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET.
IEEE J. Solid State Circuits
Jaewon Lee, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Yujin Choi, DongGeon Kim, Taekwang Jang, Gain Kim
2025 — conf
7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET.
ISSCC
Jaewon Lee, Pier Andrea Francese, Matthias Brändli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Gain Kim
2025 J jnl
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform.
IEEE Trans. Very Large Scale Integr. Syst.
Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 J jnl
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform.
IEEE Trans. Circuits Syst. II Express Briefs
Jaewon Lee, Seoyoung Jang, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 C conf
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links.
ISCAS
Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Matthias Braendli, Marcel A. Kossel, Andrea Ruffino, Thomas Morf, Pier Andrea Francese, Gain Kim
2024 J jnl
A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform.
IEEE Trans. Circuits Syst. II Express Briefs
Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Serdar A. Yonar, Matthias Braendli, Andrea Ruffino, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 J jnl
A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC.
IEEE Trans. Circuits Syst. II Express Briefs
Jaewon Lee, Seoyoung Jang, DongGeon Kim, Yujin Choi, Jong-Hyeok Yoon, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 — conf
A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links.
ISOCC
Jaewon Lee, Seoyoung Jang, DongGeon Kim, Yujin Choi, Sungyu Song, Gain Kim
2024 — conf
A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links.
ISOCC
Seoyoung Jang, Jaewon Lee, Yujin Choi, DongGeon Kim, Gain Kim
2024 J jnl
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
DongGeon Kim, Yujin Choi, Jaewon Lee, Seoyoung Jang, Sungyu Song, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024 — conf
A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator.
ICEIC
Seoyoung Jang, Jaewon Lee, Gain Kim
2024 — conf
Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics.
ICEIC
Yujin Choi, Seoyoung Jang, Gain Kim
2024 C conf
DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects.
ISCAS
Seoyoung Jang, Jaewon Lee, Yujin Choi, DongGeon Kim, Gain Kim