Seongjae Cho

30 papers Journal 27Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
Suppressing the Capacitive Coupling by Adjusting the Precharge Biasing Scheme in a Two-Transistor Dynamic Random-Access Memory Operation.
IEEE Access
Ju Hong Min, Jihun Kang, Jang Hyun Kim, Seongjae Cho
2025 J jnl
Assessment of Data Retainability of 2T DRAM for Processing-In-Memory Application.
IET Circuits Devices Syst.
Ju Hong Min, Soomin Kim, Jang Hyun Kim, Seongjae Cho
2024 — conf
Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET.
ICEIC
Soomin Kim, Seongjae Cho
2023 J jnl
A Compact Integrate-and-Fire Neuron Circuit Embedding Operational Transconductance Amplifier for Fidelity Enhancement.
IEEE Access
Arati Kumari Shah, Eou-Sik Cho, Jisun Park, Hyungsoon Shin, Seongjae Cho
2023 J jnl
An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network.
IET Circuits Devices Syst.
Arati Kumari Shah, Kannan Udaya Mohanan, Jisun Park, Hyungsoon Shin, Eou-Sik Cho, Seongjae Cho
2023 J jnl
Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application.
Appl. Intell.
Kannan Udaya Mohanan, Seongjae Cho, Byung-Gook Park
2021 J jnl
Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System.
IEEE Access
Dongyeon Kang, Jun Tae Jang, Shinyoung Park, Md. Hasan Raza Ansari, Jong-Ho Bae, Sung-Jin Choi, Dong Myong Kim, Changwook Kim, Seongjae Cho, Dae Hwan Kim
2020 J jnl
Insertion of Ag Layer in TiN/SiN
IEEE Access
Yeon-Joon Choi, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Kyungho Hong, Chae Soo Kim, Sungjun Kim, Seongjae Cho, Byung-Gook Park
2020 J jnl
Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering.
IEEE Access
Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Muhammad Ismail, Chandreswar Mahata, Teresa Oh, Muhammad Imran, Kyung Kyu Min, Tae-Hyeon Kim, Byung-Do Yang, Seongjae Cho, Byung-Gook Park, Yoon Kim, Sungjun Kim
2018 — conf
Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory.
DRC
Jae Yoon Lee, Youngmin Kim, Ikhyeon Kworn, Il Hwan Cho, Jae Yeon Lee, Soo Gil Kim, Seongjae Cho
2016 J jnl
Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell.
IEICE Trans. Electron.
Sungjun Kim, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
2015 — conf
Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect.
ISCE
Mina Yun, Seongjae Cho, Sae-Kyoung Kang, Sunghun Jung, Byung-Gook Park
2015 J jnl
Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals.
IEICE Trans. Electron.
Sungjun Kim, Sunghun Jung, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
2014 J jnl
InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate.
IEICE Trans. Electron.
Sung Yun Woo, Young Jun Yoon, Jae Hwa Seo, Gwan Min Yoo, Seongjae Cho, In Man Kang
2014 J jnl
Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access.
IEICE Electron. Express
Seongjae Cho, Sunghun Jung, Sungjun Kim, Byung-Gook Park
2012 J jnl
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance.
IEICE Electron. Express
Seongjae Cho, Hyungjin Kim, Min-Chul Sun, In Man Kang, Byung-Gook Park, James S. Harris Jr.
2011 J jnl
A New 1T DRAM Cell: Cone Type 1T DRAM Cell.
IEICE Trans. Electron.
Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park
2010 J jnl
Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs.
IEICE Electron. Express
Seongjae Cho, In Man Kang, Kyung Rok Kim
2010 J jnl
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices.
IEICE Trans. Electron.
Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park
2010 J jnl
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer.
IEICE Trans. Electron.
Dong-Seup Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jung Han Lee, Seongjae Cho, Byung-Gook Park
2009 J jnl
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array.
IEICE Trans. Electron.
Yoon Kim, Seongjae Cho, Gil Sung Lee, Il-Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2009 J jnl
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL).
IEICE Trans. Electron.
Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2009 J jnl
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era.
Microelectron. J.
Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho
2009 J jnl
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation.
IEICE Trans. Electron.
Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park
2009 J jnl
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory.
IEICE Trans. Electron.
Doo-Hyun Kim, Il-Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2008 J jnl
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.
IEICE Trans. Electron.
Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park
2008 J jnl
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI).
IEICE Trans. Electron.
Seongjae Cho, Il-Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2007 J jnl
Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs.
IEICE Trans. Electron.
Hochul Lee, Youngchang Yoon, Seongjae Cho, Hyungcheol Shin
2007 J jnl
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices.
IEICE Trans. Electron.
Seongjae Cho, Jang-Gn Yun, Il-Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
2007 J jnl
Design and Simulation of Asymmetric MOSFETs.
IEICE Trans. Electron.
Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park