Seongil O

15 papers A* 6A 2B 2Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2022 — conf
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.
ISSCC
Dae-Hyun Kim, Byungkyu Song, Hyun-A. Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee
2021 — conf
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.
ISSCC
Young-Cheon Kwon, Sukhan Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je-Min Ryu, Jong-Pil Son, Seongil O, Hak-Soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyunsung Shin, Jin Kim, BengSeng Phuah, Hyoungmin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, Sooyoung Kim, Eun-Bong Kim, David Wang, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, Joon-Ho Song, Jaeyoun Youn, Kyomin Sohn, Nam Sung Kim
2021 A* conf
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.
ISCA
Sukhan Lee, Shinhaeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, JinHyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim
2018 B conf
3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions.
PACT
Sukhan Lee, Kiwon Lee, Min Chul Sung, Mohammad Alian, Chankyung Kim, Wooyeong Cho, Reum Oh, Seongil O, Jung Ho Ahn, Nam Sung Kim
2017 A* conf
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.
HPCA
Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim
2016 J jnl
Achieving One Billion Key-Value Requests per Second on a Single Server.
IEEE Micro
Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey
2016 J jnl
Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform.
ACM Trans. Comput. Syst.
Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey
2015 A* conf
Architecting to achieve a billion requests per second throughput on a single key-value store server platform.
ISCA
Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey
2015 J jnl
CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults.
IEEE Comput. Archit. Lett.
Seongil O, Sanghyuk Kwon, Young Hoon Son, Yujin Park, Jung Ho Ahn
2015 A* conf
CiDRA: A cache-inspired DRAM resilience architecture.
HPCA
Young Hoon Son, Sukhan Lee, Seongil O, Sanghyuk Kwon, Nam Sung Kim, Jung Ho Ahn
2015 A conf
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.
ICS
Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi
2014 A conf
Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems.
SC
Young Hoon Son, Seongil O, Hyunggyun Yang, Daejin Jung, Jung Ho Ahn, John Kim, Jangwoo Kim, Jae W. Lee
2014 A* conf
Row-buffer decoupling: A case for low-latency DRAM microarchitecture.
ISCA
Seongil O, Young Hoon Son, Nam Sung Kim, Jung Ho Ahn
2013 B conf
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling.
ISPASS
Jung Ho Ahn, Sheng Li, Seongil O, Norman P. Jouppi
2013 A* conf
Reducing memory access latency with asymmetric DRAM bank organizations.
ISCA
Young Hoon Son, Seongil O, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn