SeongHwan Cho - RankMe

105 papers B 1C 9Journal 51Unranked 43

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	19.6 A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and -56dBc Worst-Case Spur Using ILO Filter in 28nm CMOS. ISSCC Jaewon Oh, Cheol So, Hyojun Kim, Songcheol Hong, SeongHwan Cho
2025	—	`conf`	37.8 A 13.5µW 35-Keyword End-to-End Keyword Spotting System Featuring Personalized On-Chip Training in 28nm CMOS. ISSCC Hyuk-Jin Lee, Kyunghoon Pyo, Taekwang Jang, Mingoo Seok, SeongHwan Cho
2025	J	`jnl`	A Fully Integrated 4:1 DC-DC Converter With Series Transmission and Parallel Reception Through Electromagnetically Coupled Class-D LC Oscillators. IEEE J. Solid State Circuits Donghyeok Cho, Taekwang Jang, SeongHwan Cho
2025	J	`jnl`	Energy-Efficient Data Transmitters Achieving Energy Per Bit Beyond CV IEEE Trans. Circuits Syst. I Regul. Pap. DongArm Shin, Youngwoo Ji, SeongHwan Cho, Taekwang Jang
2024	—	`conf`	19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur. ISSCC Hangil Choi, SeongHwan Cho
2024	—	`conf`	3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C. ISSCC Pangi Park, Junghyup Lee, SeongHwan Cho
2024	J	`jnl`	A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit. IEEE J. Solid State Circuits Jin-O. Seo, Mingoo Seok, SeongHwan Cho
2024	J	`jnl`	A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120× Multiplying Factor and 92.3-fs RMS Jitter Including Reference Spur. IEEE J. Solid State Circuits Hangil Choi, SeongHwan Cho
2024	—	`conf`	A Fully Integrated 4: 1 DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators Achieving 74.5% Peak Efficiency and 0.78W/mm² Peak Power Density. A-SSCC Donghyeok Cho, Taekwang Jang, SeongHwan Cho
2024	J	`jnl`	A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor. IEEE J. Solid State Circuits Yongjo Kim, Taekwang Jang, SeongHwan Cho
2024	J	`jnl`	A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4-ppm/ ° C From -20 °C to 125 °C. IEEE J. Solid State Circuits Pangi Park, Junghyup Lee, SeongHwan Cho
2024	—	`conf`	A Stochastic RMS Jitter Monitoring Circuit for Clock Generators using Central Limit Theorem. APCCAS Hyeonmin Park, Ahryung Kim, Jeyeon Lee, SeongHwan Cho
2024	—	`conf`	Open Ko-LLM Leaderboard: Evaluating Large Language Models in Korean with Ko-H5 Benchmark. ACL (1) Chanjun Park, Hyeonwoo Kim, Dahyun Kim, SeongHwan Cho, Sanghoon Kim, Sukyung Lee, Yungi Kim, Hwalsuk Lee
2024	J	`jnl`	Open Ko-LLM Leaderboard: Evaluating Large Language Models in Korean with Ko-H5 Benchmark. CoRR Chanjun Park, Hyeonwoo Kim, Dahyun Kim, SeongHwan Cho, Sanghoon Kim, Sukyung Lee, Yungi Kim, Hwalsuk Lee
2023	—	`conf`	A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing. VLSI Technology and Circuits Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, SeongHwan Cho, Taekwang Jang
2023	J	`jnl`	A 3.68 aF IEEE J. Solid State Circuits Sujin Park, Hyungil Chae, SeongHwan Cho
2023	J	`jnl`	A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V IEEE J. Solid State Circuits Nahmil Koo, Hyojun Kim, SeongHwan Cho
2023	—	`conf`	A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor. A-SSCC Yongjo Kim, Taekwang Jang, SeongHwan Cho
2023	J	`jnl`	A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM. IEEE J. Solid State Circuits Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho
2023	J	`jnl`	An Adaptive Filter Based Motion Artifact Cancellation Technique Using Multi-Wavelength PPG for Accurate HR Estimation. IEEE Trans. Biomed. Circuits Syst. Pangi Park, Woobean Lee, SeongHwan Cho
2023	J	`jnl`	An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. Myungjun Kim, SeongHwan Cho
2023	J	`jnl`	Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits SeongHwan Cho, Joo-Young Kim, Minoru Fujishima, Jun Zhou
2022	—	`conf`	A 2.54μJ∙ppm VLSI Technology and Circuits Seungyeob Baik, Taeryoung Seol, Sehwan Lee, Geunha Kim, SeongHwan Cho, Arup K. George, Junghyup Lee
2022	J	`jnl`	A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance. IEEE J. Solid State Circuits Sujin Park, Ji-Hwan Seol, Li Xu, SeongHwan Cho, Dennis Sylvester, David T. Blaauw
2022	J	`jnl`	A Comprehensive Analysis of Today's Malware and Its Distribution Network: Common Adversary Strategies and Implications. IEEE Access Siwon Huh, SeongHwan Cho, Jinho Choi, Seungwon Shin, Hojoon Lee
2022	—	`conf`	A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter. ISSCC Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho
2022	—	`conf`	ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory. ISSCC Jin-O. Seo, Mingoo Seok, SeongHwan Cho
2022	—	`conf`	Reduction of Motion Artifact in PPG signal with CDS-LMS Filter. APCCAS Woobean Lee, Pangi Park, SeongHwan Cho
2022	J	`jnl`	Technique for fast triangular chirp modulation in FMCW PLL. IEICE Electron. Express Han-Gil Choi, Sang Heung Lee, SeongHwan Cho
2021	—	`conf`	28.6 A 22.6µ W Biopotential Amplifier with Adaptive Common-Mode Interference Cancelation Achieving Total-CMRR of 104dB and CMI Tolerance of 15Vpp in 0.18µm CMOS. ISSCC Nahmil Koo, Hyojun Kim, SeongHwan Cho
2021	J	`jnl`	A 24.8-μW Biopotential Amplifier Tolerant to 15-V IEEE J. Solid State Circuits Nahmil Koo, SeongHwan Cho
2021	—	`conf`	A 3.68aFrms Resolution 183dB FoMs 4 VLSI Circuits Sujin Park, Hyungil Chae, SeongHwan Cho
2021	J	`jnl`	A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole. IEEE J. Solid State Circuits Myungjun Kim, SeongHwan Cho
2021	—	`conf`	An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS. A-SSCC Dongin Kim, SeongHwan Cho
2021	—	`conf`	An Energy-Efficient Voltage Step-up System for 3D NAND Flash using Charge-Compensating Regulator. VLSI Circuits Hyunsik Jeong, SeongHwan Cho
2021	C	`conf`	An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction. ISCAS Donghyeok Cho, Nahmil Koo, Taekwang Jang, SeongHwan Cho
2020	—	`conf`	A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 μm CMOS. ASP-DAC Sujin Park, Geon-Hwi Lee, Seungmin Oh, SeongHwan Cho
2019	J	`jnl`	A 2.92-µW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-µm CMOS. IEEE J. Solid State Circuits Sujin Park, Geon-Hwi Lee, SeongHwan Cho
2019	—	`conf`	A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS. ISSCC Nahmil Koo, SeongHwan Cho
2019	J	`jnl`	A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise. IEEE Trans. Circuits Syst. II Express Briefs Dongin Kim, SeongHwan Cho
2019	—	`conf`	A Low-Power Piezoelectric Speaker Driver Using LC Oscillator for Acoustic Communication. ISOCC Eunseok Lee, Sujin Park, Nahmil Koo, SeongHwan Cho
2019	J	`jnl`	A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. IEEE Trans. Circuits Syst. II Express Briefs Dongin Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho
2019	J	`jnl`	An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 µm IEEE Trans. Circuits Syst. II Express Briefs Dong-Kyun Jung, Jin-O. Seo, SeongHwan Cho
2019	—	`conf`	An On-Off Keying LC Oscillator-Based Acoustic Transmitter with Fast Turn-On and Turn-Off Time. APCCAS Eunseok Lee, Sujin Park, SeongHwan Cho
2018	—	`conf`	A 2.69UW Dual Quantization-Based Capacitance-to-Digital Converter for Pressure, Humidity, and Acceleration Sensing in 0.18UM CMOS. VLSI Circuits Sujin Park, Geon-Hwi Lee, SeongHwan Cho
2018	J	`jnl`	A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation. IEEE Trans. Very Large Scale Integr. Syst. Youngwoo Jo, Hyojun Kim, SeongHwan Cho
2018	—	`conf`	A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop. ISSCC Do-Hun Jang, SeongHwan Cho
2018	J	`jnl`	A Low-Power Photoplethysmogram-Based Heart Rate Sensor Using Heartbeat Locked Loop. IEEE Trans. Biomed. Circuits Syst. Jinseok Lee, Do-Hun Jang, Sujin Park, SeongHwan Cho
2018	—	`conf`	A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop. ASP-DAC Dongin Kim, SeongHwan Cho
2018	J	`jnl`	An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback. IEEE J. Solid State Circuits Jinseok Lee, Geon-Hwi Lee, Hyojun Kim, SeongHwan Cho
2017	J	`jnl`	A 2.3-mW 0.01-mm IEEE Trans. Circuits Syst. II Express Briefs Yongjo Kim, Keunsoo Song, Dongkyun Kim, SeongHwan Cho
2017	J	`jnl`	A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique. IEEE J. Solid State Circuits Hyunik Kim, Yongjo Kim, Taeik Kim, Hyung Jong Ko, SeongHwan Cho
2017	—	`conf`	A 255nW ultra-high input impedance analog front-end for non-contact ECG monitoring. CICC Jinseok Lee, Hyojun Kim, SeongHwan Cho
2017	—	`conf`	EE1: Student Research Preview. ISSCC SeongHwan Cho, Denis Daly
2016	—	`conf`	19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. ISSCC Hyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho
2016	J	`jnl`	A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source. IEEE Trans. Very Large Scale Integr. Syst. Young-Hwa Kim, SeongHwan Cho
2016	—	`conf`	ES1: Student research preview. ISSCC Jan Van der Spiegel, SeongHwan Cho, Denis Daly
2016	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Michael P. Flynn, Pietro Andreani, SeongHwan Cho
2015	—	`conf`	14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. ISSCC Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho
2015	—	`conf`	5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. ISSCC Junghyup Lee, Pyoungwon Park, SeongHwan Cho, Minkyu Je
2015	J	`jnl`	A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. IEEE J. Solid State Circuits Wonsik Yu, KwangSeok Kim, SeongHwan Cho
2015	J	`jnl`	A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs Jungho Kim, Young-Hwa Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho
2015	J	`jnl`	Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance. IEEE J. Solid State Circuits Woojae Lee, SeongHwan Cho
2014	J	`jnl`	A 148fs IEEE Trans. Circuits Syst. I Regul. Pap. Wonsik Yu, KwangSeok Kim, SeongHwan Cho
2014	J	`jnl`	A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. IEEE J. Solid State Circuits KwangSeok Kim, Wonsik Yu, SeongHwan Cho
2013	—	`conf`	A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. CICC Wonsik Yu, KwangSeok Kim, SeongHwan Cho
2013	J	`jnl`	A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. IEEE J. Solid State Circuits KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho
2013	J	`jnl`	A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. Wonsik Yu, Jaewook Kim, KwangSeok Kim, SeongHwan Cho
2013	—	`conf`	F5: Frequency generation and clock distribution. ISSCC Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner
2012	J	`jnl`	A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS. IEEE J. Solid State Circuits Junghyup Lee, SeongHwan Cho
2012	J	`jnl`	A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS. IEEE J. Solid State Circuits Dongmin Park, SeongHwan Cho
2012	—	`conf`	A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS. ISSCC Dongmin Park, SeongHwan Cho
2012	J	`jnl`	A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL. IEEE J. Solid State Circuits Pyoungwon Park, Dongmin Park, SeongHwan Cho
2012	J	`jnl`	A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jaewon Lee, Woojae Lee, SeongHwan Cho
2012	—	`conf`	A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. VLSIC KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho
2012	J	`jnl`	A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. Jaewon Lee, Woojae Lee, SeongHwan Cho
2012	J	`jnl`	A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration. IEEE Trans. Very Large Scale Integr. Syst. Tae-Kwang Jang, Jaewook Kim, Young-Gyu Yoon, SeongHwan Cho
2012	—	`conf`	An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. ISSCC Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho
2012	—	`conf`	Optical PCB interconnects, Niche or mainstream? ISSCC Ichiro Fujimori, SeongHwan Cho, Joshua Friedrich, John T. Stonick
2012	—	`conf`	Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee. ISSCC Ken Chang, SeongHwan Cho
2011	J	`jnl`	A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme. IEEE Trans. Very Large Scale Integr. Syst. Joonhee Lee, Sunghyun Park, SeongHwan Cho
2011	—	`conf`	A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. ISSCC Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho
2011	—	`conf`	A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL. CICC Pyoungwon Park, Dongmin Park, SeongHwan Cho
2011	—	`conf`	A time-domain flash ADC immune to voltage controlled delay line non-linearity. ASICON Young-Hwa Kim, SeongHwan Cho
2010	C	`conf`	A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. ISCAS Young-Hwa Kim, Jaewon Lee, SeongHwan Cho
2010	C	`conf`	A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS. ISCAS Woojae Lee, SeongHwan Cho
2010	C	`conf`	A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop. ISCAS Sung-Pah Lee, SeongHwan Cho
2010	J	`jnl`	An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder. IEICE Trans. Electron. Sung-Jin Kim, Min-Chang Cho, SeongHwan Cho
2010	J	`jnl`	Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Jaewook Kim, Tae-Kwang Jang, Young-Gyu Yoon, SeongHwan Cho
2010	—	`conf`	CMRR enhancement technique for IA using three IAs for bio-medical sensor applications. APCCAS Woojae Lee, Min-Chang Cho, SeongHwan Cho
2009	C	`conf`	A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13µm CMOS. ISCAS Sunghyun Park, Changwook Min, SeongHwan Cho
2009	C	`conf`	A Bio-impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity using Small Body Area. ISCAS Min-Chang Cho, Jee-Yeon Kim, SeongHwan Cho
2009	J	`jnl`	A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS. IEICE Trans. Electron. Joonhee Lee, Sungjun Kim, Sehyung Jeon, Woojae Lee, SeongHwan Cho
2009	J	`jnl`	Introduction to the Special Section on the 2008 Asian Solid-State Circuits Conference (A-SSCC'08). IEEE J. Solid State Circuits Hoi-Jun Yoo, SeongHwan Cho
2008	J	`jnl`	A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Young-Gyu Yoon, Jaewook Kim, Tae-Kwang Jang, SeongHwan Cho
2008	C	`conf`	An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder. ISCAS Sung-Jin Kim, Min-Chang Cho, Joonhyun Park, Kisuk Song, Yul Kim, SeongHwan Cho
2007	J	`jnl`	A Quadrature Modulation Transmitter Using Two Frequency Synthesizers. IEEE Trans. Circuits Syst. II Express Briefs Jaewon Lee, SeongHwan Cho
2006	B	`conf`	A Low Power Transmitter for Phase-Shift Keying Modulation Schemes. PIMRC Jaewon Lee, SeongHwan Cho
2006	C	`conf`	A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply. ISCAS Dongmin Park, SeongHwan Cho
2006	C	`conf`	A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator. ISCAS Jaewook Kim, SeongHwan Cho
2005	—	`conf`	A low power pipelined analog-to-digital converter using series sampling capacitors. ISCAS (6) SeongHwan Cho, Sungmin Ock, Sang-Hoon Lee, Joonsuk Lee
2005	—	`conf`	Variable bandwidth allocation scheme for energy efficient wireless sensor network. ICC SeongHwan Cho, Kee-Eung Kim
2004	J	`jnl`	A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications. IEEE J. Solid State Circuits SeongHwan Cho, Anantha P. Chadrakasan
2003	J	`jnl`	A behavioral modeling approach to the design of a low jitter clock source. IEEE Trans. Circuits Syst. II Express Briefs Gabriele Manganaro, Sung-Ung Kwak, SeongHwan Cho, Anurag Pulincherry
2002	—	`—`	Energy efficient radio frequency communication systems for wireless microsensors. SeongHwan Cho