Seong-Ook Jung

169 papers A* 2A 4C 8Journal 115Unranked 39

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead. IEEE J. Solid State Circuits Jungmyung Kang, Keonhee Cho, Sekeon Kim, Giseok Kim, Hyunjun Kim, Dongwook Seo, Sangyeop Baeck, Sei Seung Yoon, Seong-Ook Jung
2026	J	`jnl`	A 3× Offset, 2.9× Power, 1.3× Sensing Time, and 4× Area Reduction Direct Input Transfer Offset Cancel DRAM IO Sense Amplifier With Static Current-Free Pre-Sensing. IEEE J. Solid State Circuits Do-Yoon Lim, Sehee Lim, Dong Han Ko, In-Jun Jung, Giseok Kim, Dohan Kim, Donggyun Ha, Sunjong Park, Hohyun Chae, Seungjae Yei, Taehui Na, Seong-Ook Jung
2026	J	`jnl`	A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application. IEEE J. Solid State Circuits Sekeon Kim, Giseok Kim, Kyeongrim Baek, Keonhee Cho, Hyunjun Kim, Yeonho Jung, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung
2025	J	`jnl`	A Low-Voltage Area-Efficient TSV I/O With QEC Realizing Data Rate up to 15 Gb/s for TSV Interface. IEEE J. Solid State Circuits Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung
2025	J	`jnl`	Asymmetric Voltage Latch Type and Ultra-Low Swing Bitline Sense Amplifiers for Low-Power High-Density 1R1W 8T SRAM in 14 nm FinFET. IEEE Trans. Circuits Syst. I Regul. Pap. Giseok Kim, Keonhee Cho, Ji Sang Oh, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung
2025	—	`conf`	Design and Analysis of Static-Free PAM-4 Transmitter for HBM TSV Interface. ICEIC Jeonghyeok You, Hohyun Chae, Taeryeong Kim, Ji Hoon Lee, Seong-Ook Jung
2025	J	`jnl`	Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing. IEEE J. Solid State Circuits Sehee Lim, In Jun Jung, Gi Seok Kim, Dong Han Ko, Sumin Lee, Seong-Ook Jung
2025	—	`conf`	Multi-Modal Explainable Deep Learning-Assisted Signal Integrity Prediction Methodology. ICECS Jiyoung Yoon, Taeryeong Kim, Ki Chul Chun, Jonghoon Kim, Seong-Ook Jung
2025	J	`jnl`	SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes. IEEE Trans. Very Large Scale Integr. Syst. Keonhee Cho, Minjune Yeo, Seungjae Yei, Giseok Kim, Sangyeop Baeck, Seong-Ook Jung
2024	—	`conf`	15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node. ISSCC Minjune Yeo, Keonhee Cho, Giseok Kim, Won Joon Jo, Jisang Oh, Sekeon Kim, Kyeongrim Baek, Sungho Park, Seungjae Yei, Seong-Ook Jung
2024	J	`jnl`	A CNN-Based Super-Resolution Processor With Short-Term Caching for Real-Time UHD Upscaling. IEEE Trans. Circuits Syst. I Regul. Pap. Hong Keun Ahn, Sumin Lee, Seong-Ook Jung
2024	J	`jnl`	A Charge-Domain 4T2C eDRAM Compute-in-Memory Macro With Enhanced Variation Tolerance and Low-Overhead Data Conversion Schemes. IEEE Trans. Circuits Syst. II Express Briefs In Jun Jung, Dohan Kim, Minyoung Jo, Dong Han Ko, Young Kyu Lee, Seong-Ook Jung
2024	J	`jnl`	A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. IEEE Trans. Circuits Syst. II Express Briefs Tae-Hyun Kim, Juhyun Park, In Jun Jung, Hoonki Kim, Taejoong Song, Seong-Ook Jung
2024	—	`conf`	DPe-CIM: A 4T1C Dual-Port eDRAM Compute-in-Memory for Simultaneous Computing and Refresh with Adaptive Refresh and Data Conversion Reduction Scheme. A-SSCC Dohan Kim, Minyoung Jo, Gi-Seok Kim, Dong-Gyun Ha, Ung-Bin Oh, Seong-Ook Jung
2024	J	`jnl`	Design of Physically Unclonable Function Using Ferroelectric FET With Auto Write-Back Technique for Resource-Limited IoT Security. IEEE Internet Things J. Sehee Lim, Junghyeon Hwang, Dong Han Ko, Se Keon Kim, Tae Woo Oh, Sanghun Jeon, Seong-Ook Jung
2024	J	`jnl`	Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Sekeon Kim, Sehee Lim, Dong Han Ko, Tae Woo Oh, Seong-Ook Jung
2024	—	`conf`	Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization. ICEIC Giseok Kim, Jaehyun Park, Seong-Ook Jung
2024	J	`jnl`	Split WL 6T SRAM-Based Bit Serial Computing-in-Memory Macro With High Signal Margin and High Throughput. IEEE Trans. Circuits Syst. II Express Briefs Young Kyu Lee, Dong Han Ko, Seokhee Cho, Minjune Yeo, Mingu Kang, Seong-Ook Jung
2023	—	`conf`	A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. VLSI Technology and Circuits Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung
2023	—	`conf`	A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. VLSI Technology and Circuits Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung
2023	J	`jnl`	An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s. IEEE J. Solid State Circuits Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung
2023	J	`jnl`	An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference. IEEE Trans. Circuits Syst. II Express Briefs In Jun Jung, Tae-Hyun Kim, Keonhee Cho, Ki-Ryong Kim, Seong-Ook Jung
2023	J	`jnl`	Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Sehee Lim, Dong Han Ko, Se Keon Kim, Seong-Ook Jung
2023	J	`jnl`	Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices. IEEE J. Solid State Circuits Sehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung
2023	J	`jnl`	High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory. IEEE Trans. Circuits Syst. II Express Briefs Taeyun Lee, In Jun Jung, Seong-Ook Jung
2023	J	`jnl`	Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist. IEEE Trans. Circuits Syst. II Express Briefs Tae Woo Oh, Juhyun Park, Tae Hyun Kim, Keonhee Cho, Seong-Ook Jung
2022	—	`conf`	A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications. VLSI Technology and Circuits Keonhee Cho, Giseok Kim, Ji Sang Oh, Ki-Ryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung
2022	J	`jnl`	A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC. IEEE J. Solid State Circuits Ji-Young Kim, Jongsoo Lee, Ki-Ryong Kim, Sunghwan Jo, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung
2022	—	`conf`	A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF. ESSCIRC Sehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Minki Kim, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung
2022	—	`conf`	A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. VLSI Technology and Circuits Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung
2022	J	`jnl`	A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array. IEEE Trans. Circuits Syst. I Regul. Pap. Tae-Hyun Kim, Byungkyu Song, In Jun Jung, Seong-Ook Jung
2022	—	`conf`	SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm ESSCIRC Sumin Lee, Ki-Beom Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee, Dohyung Kim, Bumsub Ham, Seong-Ook Jung
2022	J	`jnl`	SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation. IEEE Trans. Circuits Syst. II Express Briefs Keonhee Cho, Juhyun Park, Ki-Ryong Kim, Tae Woo Oh, Seong-Ook Jung
2022	J	`jnl`	SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling. IEEE J. Solid State Circuits Keonhee Cho, Heekyung Choi, In Jun Jung, Ji Sang Oh, Tae Woo Oh, Ki-Ryong Kim, Giseok Kim, Taemin Choi, Changsu Sim, Taejoong Song, Seong-Ook Jung
2021	J	`jnl`	A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With V IEEE Trans. Circuits Syst. II Express Briefs Ji-Young Kim, Jongsoo Lee, Ki-Ryong Kim, Byoung-Mo Moon, Seong-Ook Jung
2021	J	`jnl`	A 6.9-μm IEEE Trans. Circuits Syst. II Express Briefs Ki-Ryong Kim, Ji Young Kim, Byoung-Mo Moon, Seong-Ook Jung
2021	J	`jnl`	A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. IEEE J. Solid State Circuits Hanwool Jeong, Tae Hyun Kim, Changnam Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung
2021	J	`jnl`	Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM. IEEE Trans. Very Large Scale Integr. Syst. Kwang Woo Lee, Hyun Kook Park, Seong-Ook Jung
2021	J	`jnl`	All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash. IEEE Access Jun Ho An, Jin Young Chun, Hyun Kook Park, Seong-Ook Jung
2021	J	`jnl`	Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM. IEEE Access Ki-Ryong Kim, Tae Woo Oh, Seong-Ook Jung
2021	—	`conf`	CNN encryption using XOR Gate for Hardware Optimization. ISOCC Ki Beom Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung
2021	J	`jnl`	Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells. IEEE Access Dong Han Ko, Tae Woo Oh, Sehee Lim, Se Keon Kim, Seong-Ook Jung
2021	J	`jnl`	Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation. IEEE Access Ji Sang Oh, Juhyun Park, Keonhee Cho, Tae Woo Oh, Seong-Ook Jung
2021	J	`jnl`	Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique. IEEE Trans. Inf. Forensics Secur. Byungkyu Song, Sehee Lim, Seung-Hyuk Kang, Seong-Ook Jung
2021	—	`conf`	High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. ISOCC Dong Han Ko, Sehee Lim, Young Kyu Lee, Seong-Ook Jung
2021	J	`jnl`	High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops. IEEE Access Se Keon Kim, Tae Woo Oh, Sehee Lim, Dong Han Ko, Seong-Ook Jung
2021	J	`jnl`	Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Suk Min Kim, Byungkyu Song, Seong-Ook Jung
2021	—	`conf`	Intrinsic Capacitance based Multi bit Computing in Memory. ISOCC Young Kyu Lee, Minjune Yeo, Seokhee Cho, Seong-Ook Jung
2021	—	`conf`	SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. VLSI Circuits Keonhee Cho, Heekyung Choi, In Jun Jung, Ji Sang Oh, Tae Woo Oh, Ki-Ryong Kim, Giseok Kim, Taemin Choi, Changsoo Sim, Taejoong Song, Seong-Ook Jung
2021	J	`jnl`	STT-MRAM Sensing: A Review. IEEE Trans. Circuits Syst. II Express Briefs Taehui Na, Seung-Hyuk Kang, Seong-Ook Jung
2021	J	`jnl`	Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. Sara Choi, Hong Keun Ahn, Byungkyu Song, Seung-Hyuk Kang, Seong-Ook Jung
2020	J	`jnl`	A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM. IEEE Trans. Very Large Scale Integr. Syst. Hyun Kook Park, Hong Keun Ahn, Seong-Ook Jung
2020	C	`conf`	A Read Voltage Modulation Technique for Leakage Current Compensation in Cross-Point OTS-PRAM. ISCAS Kwang Woo Lee, Hyun Kook Park, Seong-Ook Jung
2020	J	`jnl`	An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. IEEE Access Tae Hyun Kim, Hanwool Jeong, Juhyun Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung
2020	J	`jnl`	Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC. IEEE Access Giseok Kim, Ki-Ryong Kim, Sara Choi, Hyo Jung Jang, Seong-Ook Jung
2020	J	`jnl`	CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution. IEEE Access Sumin Lee, Sunghwan Jo, Hong Keun Ahn, Seong-Ook Jung
2020	J	`jnl`	Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit. Sensors Jongha Park, Jung-Hyun Park, Seong-Ook Jung
2020	J	`jnl`	Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability. IEEE Trans. Inf. Forensics Secur. Sehee Lim, Byungkyu Song, Seong-Ook Jung
2020	J	`jnl`	One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Keonhee Cho, Juhyun Park, Tae Woo Oh, Seong-Ook Jung
2020	J	`jnl`	pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation. IEEE Trans. Very Large Scale Integr. Syst. Juhyun Park, Tae Woo Oh, Seong-Ook Jung
2019	J	`jnl`	A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories. IEEE Trans. Very Large Scale Integr. Syst. Sara Choi, Hong Keun Ahn, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2019	J	`jnl`	Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving. IEEE J. Solid State Circuits Hanwool Jeong, Se Hyeok Oh, Tae Woo Oh, Hoonki Kim, Changnam Park, Woojin Rim, Taejoong Song, Seong-Ook Jung
2019	J	`jnl`	Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Taehui Na, Byungkyu Song, Sara Choi, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2019	J	`jnl`	Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region. IEEE Trans. Circuits Syst. I Regul. Pap. Byungkyu Song, Sara Choi, Seung-Hyuk Kang, Seong-Ook Jung
2019	J	`jnl`	Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time. IEEE J. Solid State Circuits Hanwool Jeong, Juhyun Park, Seung Chul Song, Seong-Ook Jung
2019	J	`jnl`	Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM. IEEE Trans. Very Large Scale Integr. Syst. Suk Min Kim, Byungkyu Song, Seong-Ook Jung
2019	J	`jnl`	Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung
2018	J	`jnl`	0.293-mm IEEE J. Solid State Circuits Dong-Hoon Jung, Ki-Ryong Kim, Sunghwan Jo, Seong-Ook Jung
2018	—	`conf`	A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation. ICECS Hyun Kook Park, Tae Woo Oh, Seong-Ook Jung
2018	J	`jnl`	All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate. IEEE Trans. Very Large Scale Integr. Syst. Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2018	—	`conf`	Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. PRIME Suk Min Kim, Byungkyu Song, Tae Woo Oh, Seong-Ook Jung
2018	J	`jnl`	Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2018	C	`conf`	SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation. ISCAS Tae Woo Oh, Seong-Ook Jung
2018	J	`jnl`	Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation. IEEE Trans. Very Large Scale Integr. Syst. Hanwool Jeong, Tae Woo Oh, Seung Chul Song, Seong-Ook Jung
2018	—	`conf`	Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic Synapse. ICECS Beomsang Yoo, Ki-Ryong Kim, Seong-Ook Jung
2017	J	`jnl`	A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area. IEEE Trans. Circuits Syst. II Express Briefs Byungkyu Song, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2017	J	`jnl`	GRO-TDC with gate-switch-based delay cell halving resolution limit. Int. J. Circuit Theory Appl. Jung-Hyun Park, Dong-Hoon Jung, Seong-Ook Jung
2017	J	`jnl`	Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Junyoung Ko, Younghwi Yang, Jisu Kim, Younghoon Oh, Hyun Kook Park, Seong-Ook Jung
2017	J	`jnl`	Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS. IEEE J. Solid State Circuits Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2017	J	`jnl`	Power-Gated 9T SRAM Cell for Low-Energy Operation. IEEE Trans. Very Large Scale Integr. Syst. Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, Seong-Ook Jung
2017	J	`jnl`	Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Tae Woo Oh, Hanwool Jeong, Juhyun Park, Seong-Ook Jung
2017	J	`jnl`	SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. Tae Hoon Choi, Hanwool Jeong, Younghwi Yang, Juhyun Park, Seong-Ook Jung
2016	J	`jnl`	All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme. IEEE Trans. Very Large Scale Integr. Syst. Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2016	J	`jnl`	All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator. IEEE Trans. Very Large Scale Integr. Syst. Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Hyuck-Sang Yim, Seong-Ook Jung
2016	J	`jnl`	An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. Taehui Na, Jisu Kim, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2016	C	`conf`	Area-optimal sensing circuit designs in deep submicrometer STT-RAM. ISCAS Sara Choi, Taehui Na, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang
2016	J	`jnl`	Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. IEEE Trans. Circuits Syst. II Express Briefs Hanwool Jeong, Juhyun Park, Tae Woo Oh, Woojin Rim, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung
2016	J	`jnl`	Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. Sara Choi, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2016	—	`conf`	Equalization scheme analysis for high-density spin transfer torque random access memory. ISOCC Beomsang Yoo, Taehui Na, Byungkyu Song, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang
2016	J	`jnl`	Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation. IEEE Trans. Very Large Scale Integr. Syst. Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Ki-Ryong Kim, Seong-Ook Jung
2016	J	`jnl`	High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin Hyuk Kim, Seong-Ook Jung
2016	J	`jnl`	Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2016	J	`jnl`	Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. II Express Briefs Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2016	J	`jnl`	Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2016	J	`jnl`	Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm. IEICE Electron. Express Dong-Hoon Jung, Ki-Ryong Kim, Seong-Ook Jung
2016	J	`jnl`	Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution. IEEE Trans. Circuits Syst. II Express Briefs Ki-Ryong Kim, Hanwool Jeong, Juhyun Park, Seong-Ook Jung
2016	C	`conf`	WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. ISCAS Junyoung Ko, Younghwi Yang, Seong-Ook Jung, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim
2015	J	`jnl`	A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory. IEEE Trans. Circuits Syst. II Express Briefs Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2015	J	`jnl`	All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM. IEEE Trans. Circuits Syst. II Express Briefs Dong-Hoon Jung, Young-Jae An, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2015	J	`jnl`	An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management. IEEE Trans. Very Large Scale Integr. Syst. Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Seung-Han Woo, Seong-Ook Jung
2015	J	`jnl`	Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. IEEE Trans. Very Large Scale Integr. Syst. Heechai Kang, Jisu Kim, Hanwool Jeong, Younghwi Yang, Seong-Ook Jung
2015	—	`conf`	Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter. ICECS Taehui Na, Hanwool Jeong, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang
2015	J	`jnl`	Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. Byungkyu Song, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2015	J	`jnl`	Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs. IEEE Trans. Very Large Scale Integr. Syst. Jung-Hyun Park, Heechai Kang, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung
2015	J	`jnl`	Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectron. J. Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung
2015	J	`jnl`	Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Hanwool Jeong, Taewon Kim, Younghwi Yang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung
2015	A	`conf`	Reference-circuit analysis for high-bandwidth spin transfer torque random access memory. ISLPED Byungkyu Song, Taehui Na, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang
2015	J	`jnl`	SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2015	J	`jnl`	Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Younghwi Yang, Juhyun Park, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung
2015	J	`jnl`	Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Hanwool Jeong, Taewon Kim, Kyoman Kang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung
2015	J	`jnl`	Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Junyoung Ko, Jisu Kim, Youngdon Choi, Hyun Kook Park, Seong-Ook Jung
2015	J	`jnl`	Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. IEEE Trans. Very Large Scale Integr. Syst. Hanwool Jeong, Taewon Kim, Taejoong Song, Gyu-Hong Kim, Seong-Ook Jung
2014	J	`jnl`	A Split-Path Sensing Circuit for Spin Torque Transfer MRAM. IEEE Trans. Circuits Syst. II Express Briefs Jisu Kim, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2014	J	`jnl`	An MTJ-based non-volatile flip-flop for high-performance SoC. Int. J. Circuit Theory Appl. Youngdon Jung, Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2014	J	`jnl`	An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2014	J	`jnl`	Comparative Study of Various Latch-Type Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. Taehui Na, Seung-Han Woo, Jisu Kim, Hanwool Jeong, Seong-Ook Jung
2014	C	`conf`	High-performance low-power magnetic tunnel junction based non-volatile flip-flop. ISCAS Taehui Na, Kyungho Ryu, Jisu Kim, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang
2014	J	`jnl`	One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM. IEEE Trans. Very Large Scale Integr. Syst. Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung
2014	J	`jnl`	Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector. IEEE Trans. Circuits Syst. II Express Briefs Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung
2014	—	`conf`	Pseudo NMOS based sense amplifier for high speed single-ended SRAM. ICECS Hanwool Jeong, Taewon Kim, Seong-Ook Jung, Taejoong Song, Gyu-Hong Kim
2014	J	`jnl`	Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM. IEEE Trans. Circuits Syst. I Regul. Pap. Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2014	J	`jnl`	STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies. IEEE Trans. Very Large Scale Integr. Syst. Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2013	C	`conf`	A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management. ICCE Young-Jae An, Kyungho Ryu, Dong-Hoon Jung, Seung-Han Woo, Seong-Ook Jung
2013	C	`conf`	A comparative study of STT-MTJ based non-volatile flip-flops. ISCAS Taehui Na, Kyungho Ryu, Jisu Kim, Seung-Hyuk Kang, Seong-Ook Jung
2013	J	`jnl`	ADDLL for Clock-Deskew Buffer in High-Performance SoCs. IEEE Trans. Very Large Scale Integr. Syst. Jung-Hyun Park, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung
2013	—	`conf`	All-digital 90° phase-shift DLL with a dithering jitter suppression scheme. CICC Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Won Lee, Seong-Ook Jung
2013	—	`conf`	All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. ESSCIRC Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung
2013	J	`jnl`	Dynamic mixed serial-parallel content addressable memory (DMSP CAM). Int. J. Circuit Theory Appl. Mingu Kang, Jisu Kim, Younghwi Yang, Seong-Ook Jung
2012	J	`jnl`	A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung
2012	J	`jnl`	A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop. IEEE Trans. Very Large Scale Integr. Syst. Kyungho Ryu, Jisu Kim, Jiwan Jung, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung
2012	J	`jnl`	A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). IEEE Trans. Very Large Scale Integr. Syst. Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung
2012	—	`conf`	A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. ESSCIRC Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2012	—	`conf`	Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM. ISOCC Junha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-Ook Jung
2012	—	`conf`	Integration of dual channel timing formatter system for high speed memory test equipment. ISOCC Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang
2012	J	`jnl`	Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. IEEE Trans. Circuits Syst. I Regul. Pap. Heechai Kang, Kyungho Ryu, Dong-Hoon Jung, Donghwan Lee, Won Lee, Suho Kim, JongRyun Choi, Seong-Ook Jung
2012	—	`conf`	Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits. ICECS Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung
2011	—	`conf`	MTJ based non-volatile flip-flop in deep submicron technology. ISOCC Youngdon Jung, Jisu Kim, Kyungho Ryu, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang
2011	J	`jnl`	Sensing margin trend with technology scaling in MRAM. Int. J. Circuit Theory Appl. Jee-Hwan Song, Jisu Kim, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung
2010	J	`jnl`	A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface. IEEE Trans. Consumer Electron. Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung
2010	J	`jnl`	A DLL based clock generator for low-power mobile SoCs. IEEE Trans. Consumer Electron. Kyungho Ryu, Dong Hun Jung, Seong-Ook Jung
2010	J	`jnl`	Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits. IEICE Trans. Electron. Jisu Kim, Jee-Hwan Song, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung
2010	—	`conf`	Process variation tolerant all-digital multiphase DLL for DDR3 interface. CICC Heechai Kang, Kyungho Ryu, Donghwan Lee, Won Lee, Suho Kim, JongRyun Choi, Seong-Ook Jung
2009	J	`jnl`	Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mingu Kang, Seong-Ook Jung
2009	J	`jnl`	Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. IEEE Trans. Circuits Syst. I Regul. Pap. Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy
2008	J	`jnl`	Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation. IEEE Trans. Circuits Syst. II Express Briefs Hyunwoo Nho, Sei-Seung Yoon, S. Simon Wong, Seong-Ook Jung
2008	J	`jnl`	Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Seong-Ook Jung, Sei-Seung Yoon
2007	A	`conf`	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ISLPED Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy
2006	—	`conf`	Thyristor-Based Volatile Memory in Nano-Scale CMOS. ISSCC Rich Roy, Farid Nemati, Ken Young, Bruce Bateman, Rajesh Chopra, Seong-Ook Jung, Chiming Show, Hyun-jin Cho
2005	J	`jnl`	A 32-bit carry lookahead adder using dual-path all-N logic. IEEE Trans. Very Large Scale Integr. Syst. Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
2004	—	`conf`	A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. ISCAS (2) Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
2003	J	`jnl`	Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
2003	J	`jnl`	Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
2003	J	`jnl`	Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
2003	J	`jnl`	Timing constraints for domino logic gates with timing-dependent keepers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002	A	`conf`	Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. DATE Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002	—	`—`	Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology Seong-Ook Jung
2002	A*	`conf`	Low-swing clock domino logic incorporating dual supply and dual threshold voltages. DAC Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002	J	`jnl`	Noise constrained transistor sizing and power optimization for dual Vs IEEE Trans. Very Large Scale Integr. Syst. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002	—	`conf`	Optimal Timing for Skew-Tolerant High-Speed Domino Logic. ISVLSI Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2001	—	`conf`	2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. ACM Great Lakes Symposium on VLSI Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
2001	A*	`conf`	Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
2001	—	`conf`	Coupling-aware minimum delay optimization for domino logic circuits. ISCAS (5) Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang
2001	—	`conf`	Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. ISCAS (4) Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
2001	—	`conf`	New current-mode sense amplifiers for high density DRAM and PIM architectures. ISCAS (4) Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
2001	—	`conf`	Noise constrained power optimization for dual VT domino logic. ISCAS (4) Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2001	—	`conf`	Skew-tolerant high-speed (STHS) domino logic. ISCAS (4) Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang
2001	—	`conf`	Transistor sizing for reliable domino logic design in dual threshold voltage technologies. ACM Great Lakes Symposium on VLSI Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2000	A	`conf`	Noise-aware power optimization for on-chip interconnect. ISLPED Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
2000	C	`conf`	Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic. ISCAS Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang