Seokhyeong Kang

134 papers A* 15A 36C 5Journal 32Unranked 45

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A Heterogeneous Graph-based Gate Sizer Integrating Graph Attention Network and Transformer. ASP-DAC Jinmo Ahn, Jinoh Cho, Jaemin Seo, Jaeseung Lee, Jakang Lee, Seokhyeong Kang
2026	—	`conf`	Au-MEDAL: Adaptable Grid Router with Metal Edge Detection And Layer Integration. ASP-DAC Andrew B. Kahng, Seokhyeong Kang, Sehyeon Kim, Jakang Lee, Dooseok Yoon
2026	J	`jnl`	CTRL-B: Back-End-of-Line Configuration Optimization Using Cross-Domain Transferable Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeseung Lee, Sung-Yun Lee, Jinoh Cho, Daijoon Hyun, Seokhyeong Kang
2026	—	`conf`	Invited: Post-Placement Buffering and Sizing Contest. ISPD Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Yiting Liu, Davit Markarian, SeongHyeon Park, Zhiang Wang
2026	—	`conf`	REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models. ASP-DAC Kyungjun Min, Kyumin Cho, Junhwan Jang, Seokhyeong Kang
2025	A	`conf`	A Parallel Analytical Legalization Algorithm via Alternating Direction Method of Multipliers. ICCAD Jaekyung Im, Seokhyeong Kang
2025	J	`jnl`	ArtNet: Hierarchical Clustering-Based Artificial Netlist Generator for ML and DTCO Application. CoRR Andrew B. Kahng, Seokhyeong Kang, SeongHyeon Park, Dooseok Yoon
2025	A	`conf`	Diffusion-Enhanced Graph Transformer with Reinforcement Learning for Transferable Analog Circuit Optimizer. ISLPED Ho-jin Lee, Kyeong-Jun Lee, Jae-Hoon Lee, Kyu-Jin Choi, Geunyong Choi, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang, Jae-Yoon Sim
2025	A	`conf`	Enhancing Timing Closure via Spatially Embedded Graph Transformer with Low Power/Area Overhead. ICCAD Joonyoung Seo, Jonghyeon Nam, Howoo Jang, Yoonseok Jung, Seokhyeong Kang
2025	A*	`conf`	FedEDA: Federated Learning Framework for Privacy-Preserving Machine Learning in EDA. DAC Joonseok Kim, Donggyu Kim, SeongHyeon Park, Seokhyeong Kang
2025	A	`conf`	Improving LLM-Based Verilog Code Generation with Data Augmentation and RL. DATE Kyungjun Min, SeongHyeon Park, Hyeonwoo Park, Jinoh Cho, Seokhyeong Kang
2025	—	`conf`	Invited: Artificial Netlist Generation for Enhanced Circuit Data Augmentation. ISPD Seokhyeong Kang
2025	—	`conf`	LIBMixer: An all-MLP Architecture for Cell Library Characterization towards Design Space Optimization. ASP-DAC Jaeseung Lee, Sunggyu Jang, Jakang Lee, Seokhyeong Kang
2025	A*	`conf`	Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation. DAC Jongho Yoon, Jinsung Jeon, Seokhyeong Kang
2025	A*	`conf`	Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation. DAC Hyeonwoo Park, SeongHyeon Park, Seokhyeong Kang
2025	—	`conf`	Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement. ASP-DAC Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, SeongHyeon Park, Jaemin Seo, Jongho Yoon, Seokhyeong Kang
2025	A	`conf`	Neural Circuit Parameter Prediction for Efficient Quantum Data Loading. DATE Dohun Kim, Sunghye Park, Seokhyeong Kang
2025	—	`conf`	PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog Circuits. ASP-DAC Youngchang Choi, Sejin Park, Ho-jin Lee, Kyongsu Lee, Jae-Yoon Sim, Seokhyeong Kang
2025	—	`conf`	ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC Prediction. ASP-DAC Jongho Yoon, Jakang Lee, Donggyu Kim, Junseok Hur, Seokhyeong Kang
2025	J	`jnl`	REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models. CoRR Kyungjun Min, Kyumin Cho, Junhwan Jang, Seokhyeong Kang
2025	A	`conf`	SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing. ICCAD Chung-Kuan Cheng, Andrew B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin
2024	A	`conf`	CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning. DATE Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
2024	A*	`conf`	HiLight: A Comprehensive Framework for High-Performance and Lightweight Scalability in Surface Code Communication. DAC Sunghye Park, Dohun Kim, Seokhyeong Kang
2024	A	`conf`	Improvement of Mixed Track - Height Standard-Cell Placement. DATE Andrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon
2024	A	`conf`	Improving Timing & Power Trade-off in Post-place Optimization Using Multi-agent Reinforcement Learning. ICCAD Jaemin Seo, Sejin Park, Seokhyeong Kang
2024	J	`jnl`	MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors. IEEE Trans. Circuits Syst. I Regul. Pap. Youngchang Choi, Sejin Park, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang
2024	J	`jnl`	Mobile Transformer Accelerator Exploiting Various Line Sparsity and Tile-Based Dynamic Quantization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eunji Kwon, Jongho Yoon, Seokhyeong Kang
2024	A*	`conf`	PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. DAC Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Kyungjun Min, SeongHyeon Park, Bodhisatta Pramanik
2024	—	`conf`	QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization. ISQED Seongbin Kwon, Dohun Kim, Sunghye Park, Seojeong Kim, Seokhyeong Kang
2024	A	`conf`	RL-Fill: Timing-Aware Fill Insertion using Reinforcement Learning. ICCAD Jinoh Cho, SeongHyeon Park, Jakang Lee, Sung-Yun Lee, Jinmo Ahn, Seokhyeong Kang
2024	A*	`conf`	RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers. DAC Eunji Kwon, Minxuan Zhou, Weihong Xu, Tajana Rosing, Seokhyeong Kang
2024	A*	`conf`	SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation. DAC Jaekyung Im, Seokhyeong Kang
2024	—	`conf`	TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path. MLCAD Donggyu Kim, Minjae Kim, Junseok Hur, Jakang Lee, Jinoh Cho, Seokhyeong Kang
2024	A	`conf`	Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation. DATE Ho-jin Lee, Kyeong-Jun Lee, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang, Jae-Yoon Sim
2024	A	`conf`	Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space Optimization. DATE Jaemin Seo, Sejin Park, Seokhyeong Kang
2024	A	`conf`	ViT- ToGo: Vision Transformer Accelerator with Grouped Token Pruning. DATE Seungju Lee, Kyumin Cho, Eunji Kwon, Sejin Park, Seojeong Kim, Seokhyeong Kang
2023	—	`conf`	Advanced Parasitic Capacitance Extraction using Active Learning. ISOCC Donggyu Kim, Jakang Lee, Seokhyeong Kang
2023	A	`conf`	ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks. ICCAD Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang
2023	J	`jnl`	Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daeyeon Kim, Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
2023	A	`conf`	FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks. DATE Haena Song, Jongho Yoon, Dohun Kim, Eunji Kwon, Tae-Hyun Oh, Seokhyeong Kang
2023	—	`conf`	Graph Partitioning Approach for Fast Quantum Circuit Simulation. ASP-DAC Jaekyung Im, Seokhyeong Kang
2023	J	`jnl`	Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers. CoRR Ludwig Schmid, Sunghye Park, Seokhyeong Kang, Robert Wille
2023	—	`conf`	Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization. SLIP SeongHyeon Park, Daeyeon Kim, Seokhyeong Kang
2023	A	`conf`	MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors. DATE Youngchang Choi, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang
2023	—	`conf`	Machine Learning-based Fast Circuit Simulation for Analog Circuit Array. MLCAD Jaeseung Lee, Sejin Park, Minhyeok Kweon, Seokhyeong Kang
2023	A	`conf`	Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision. DATE Eunji Kwon, Haena Song, Jihye Park, Seokhyeong Kang
2023	A	`conf`	Multi-Source Transfer Learning for Design Technology Co-Optimization. ISLPED Jakang Lee, Jaeseung Lee, SeongHyeon Park, Seokhyeong Kang
2023	J	`jnl`	Optimizing Ternary Multiplier Design With Fast Ternary Adder. IEEE Trans. Circuits Syst. II Express Briefs Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang
2023	—	`conf`	Placement Initialization via Community Detection. ISOCC Junseok Hur, Jaekyung Im, Seokhyeong Kang
2023	A	`conf`	RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization. DATE Sung-Yun Lee, SeongHyeon Park, Daeyeon Kim, Minjae Kim, Tuyen Pham Le, Seokhyeong Kang
2023	A*	`conf`	Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing. DAC Minjeong Choi, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang
2023	A	`conf`	Routability Prediction and Optimization Using Explainable AI. ICCAD SeongHyeon Park, Daeyeon Kim, Seongbin Kwon, Seokhyeong Kang
2023	A	`conf`	Routability Prediction using Deep Hierarchical Classification and Regression. DATE Daeyeon Kim, Jakang Lee, Seokhyeong Kang
2023	—	`conf`	Soft Actor-Critic Reinforcement Learning-Based Optimization for Analog Circuit Sizing. ISOCC Sejin Park, Youngchang Choi, Seokhyeong Kang
2022	J	`jnl`	A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit. IEEE J. Solid State Circuits Kiseo Kang, Donggyu Minn, Seongun Bae, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Jae-Yoon Sim
2022	—	`conf`	A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits. ISSCC Kiseo Kang, Donggyu Minn, Seunghun Bae, Jaeho Lee, Seongun Bae, Gichang Jung, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Jae-Yoon Sim
2022	A*	`conf`	A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers. DAC Sunghye Park, Daeyeon Kim, Minhyuk Kweon, Jae-Yoon Sim, Seokhyeong Kang
2022	—	`conf`	Adaptive FSP: Adaptive Architecture Search with Filter Shape Pruning. ACCV (1) Aeri Kim, Seungju Lee, Eunji Kwon, Seokhyeong Kang
2022	J	`jnl`	CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. Hyeokjun Kwon, Younghoon Byun, Seokhyeong Kang, Youngjoo Lee
2022	C	`conf`	CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping. ICCD Jihye Park, Seokhyeong Kang
2022	A	`conf`	Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. DATE Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee
2022	—	`conf`	GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN. ACM Great Lakes Symposium on VLSI Myong Kong, Daeyeon Kim, Minhyuk Kweon, Seokhyeong Kang
2022	J	`jnl`	Lightweight Speaker Recognition in Poincaré Spaces. IEEE Signal Process. Lett. Jieun Lee, Sung-Bin Kim, Seokhyeong Kang, Tae-Hyun Oh
2022	A	`conf`	MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device. ICCAD Sunghye Park, Dohun Kim, Jae-Yoon Sim, Seokhyeong Kang
2022	—	`conf`	Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration. ASP-DAC Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang
2021	—	`conf`	A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers. VLSI Circuits Kiseo Kang, Byungjun Kim, Gahyun Choi, Sun-Kyung Lee, Jisoo Choi, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Yonuk Chong, Jae-Yoon Sim
2021	A	`conf`	Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks. DATE Yesung Kang, Eunji Kwon, Seunggyu Lee, Younghoon Byun, Youngjoo Lee, Seokhyeong Kang
2021	—	`conf`	Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. ISOCC Jaekyung Im, Seokhyeong Kang
2021	—	`conf`	Components Analysis on Audio Signal Mixtures. ISOCC Chanhee Lee, Sangho Yoon, Seokhyeong Kang
2021	—	`conf`	Data Protection Method for Flash Memory in Serial Peripheral Interface. ISOCC Aeri Kim, Seokhyeong Kang
2021	C	`conf`	Design and Analysis of a Low-Power Ternary SRAM. ISCAS Youngchang Choi, Sunmean Kim, Kyongsu Lee, Seokhyeong Kang
2021	J	`jnl`	Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. CoRR Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee
2021	J	`jnl`	Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology. IEEE Trans. Very Large Scale Integr. Syst. Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Bangqi Xu
2021	J	`jnl`	Fluctuation-Based Fade Detection for Local Scene Changes. IEEE Access Sangho Yoon, Chanhee Lee, Ho Sub Lee, Young Hwan Kim, Seokhyeong Kang
2021	—	`conf`	Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM. ISOCC Seunggyu Lee, Jongho Yoon, Jakang Lee, Seokhyeong Kang
2021	J	`jnl`	Low-Power Ternary Multiplication Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs Sunmean Kim, Yesung Kang, Seunghan Baek, Youngchang Choi, Seokhyeong Kang
2021	A	`conf`	MDARTS: Multi-objective Differentiable Neural Architecture Search. DATE Sunghoon Kim, Hyun-jeong Kwon, Eunji Kwon, Youngchang Choi, Tae-Hyun Oh, Seokhyeong Kang
2021	A	`conf`	Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator. DATE Daeyeon Kim, Hyun-jeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang
2021	—	`conf`	Memcapacitor based Minimum and Maximum Gate Design. ISOCC Jiyoung Min, Sunmean Kim, Seokhyeong Kang
2021	J	`jnl`	Reinforcement Learning-Based Power Management Policy for Mobile Device Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Eunji Kwon, Sodam Han, Yoonho Park, Jongho Yoon, Seokhyeong Kang
2021	—	`conf`	Ternary Sense Amplifier Design for Ternary SRAM. ISOCC Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang
2021	J	`jnl`	Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. Hyun-jeong Kwon, Daeyeon Kim, Young Hwan Kim, Seokhyeong Kang
2020	J	`jnl`	A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang
2020	J	`jnl`	Additive Statistical Leakage Analysis Using Exponential Mixture Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyun-jeong Kwon, Sung-Yun Lee, Young Hwan Kim, Seokhyeong Kang
2020	A	`conf`	Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling. DATE Yesung Kang, Yoonho Park, Sunghoon Kim, Eunji Kwon, Taeho Lim, Sangyun Oh, Mingyu Woo, Seokhyeong Kang
2020	J	`jnl`	Compact Topology-Aware Bus Routing for Design Regularity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daeyeon Kim, SangGi Do, Sung-Yun Lee, Seokhyeong Kang
2020	—	`conf`	Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. ISMVL Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, Byoung Hun Lee
2020	A	`conf`	GRLC: grid-based run-length compression for energy-efficient CNN accelerator. ISLPED Yoonho Park, Yesung Kang, Sunghoon Kim, Eunji Kwon, Seokhyeong Kang
2020	A*	`conf`	Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device Systems. DAC Eunji Kwon, Sodam Han, Yoonho Park, Young Hwan Kim, Seokhyeong Kang
2020	—	`conf`	Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. ISOCC Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang
2020	—	`conf`	MTCMOS-based Ternary to Binary Converter. ISOCC Seunghan Baek, Sunmean Kim, Youngchang Choi, Seokhyeong Kang
2020	J	`jnl`	Proactive Scenario Characteristic-Aware Online Power Management on Mobile Systems. IEEE Access Sodam Han, Yonghee Yun, Young Hwan Kim, Seokhyeong Kang
2019	—	`conf`	Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. ISMVL Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
2019	—	`conf`	Fence-Region-Aware Mixed-Height Standard Cell Legalization. ACM Great Lakes Symposium on VLSI SangGi Do, Mingyu Woo, Seokhyeong Kang
2019	—	`conf`	Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU. ISOCC Sunghye Park, Sunmean Kim, Seokhyeong Kang
2019	—	`conf`	Outlier-aware Time-multiplexing MAC for Higher Energy-Efficiency on CNNs. ISOCC Eunji Kwon, Yesung Kang, Seokhyeong Kang
2019	A	`conf`	Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology. DATE Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi, Bangqi Xu
2019	J	`jnl`	Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems. IEEE Access Seungwon Kim, Ki Jin Han, Youngmin Kim, Seokhyeong Kang
2019	J	`jnl`	SmartGrid: Video Retargeting With Spatiotemporal Grid Optimization. IEEE Access Ho Sub Lee, Gyu Jin Bae, Sung In Cho, Young Hwan Kim, Seokhyeong Kang
2019	—	`conf`	Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm. ISMVL Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang
2018	—	`conf`	An optimal gate design for the synthesis of ternary logic circuits. ASP-DAC Sunmean Kim, Taeho Lim, Seokhyeong Kang
2018	—	`conf`	Estimation of Leakage Distribution Utilizing Gaussian Mixture Model. ISOCC Hyun-jeong Kwon, Young Hwan Kim, Seokhyeong Kang
2018	A	`conf`	Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study. DATE Seungwon Kim, Ki Jin Han, Youngmin Kim, Seokhyeong Kang
2018	J	`jnl`	SoftCorner: Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems. IEEE Access Hyun-jeong Kwon, Jae Hoon Kim, Seokhyeong Kang, Young Hwan Kim
2018	J	`jnl`	Statistical Leakage Analysis Using Gaussian Mixture Model. IEEE Access Hyun-jeong Kwon, Mingyu Woo, Young Hwan Kim, Seokhyeong Kang
2017	—	`conf`	A Novel Ternary Multiplier Based on Ternary CMOS Compact Model. ISMVL Yesung Kang, Jaewoo Kim, Sunmin Kim, Sunhae Shin, E-San Jang, Jae Won Jeong, Kyung Rok Kim, Seokhyeong Kang
2017	A*	`conf`	Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization. DAC Seungwon Kim, SangGi Do, Seokhyeong Kang
2017	A	`conf`	GRASP based metaheuristics for layout pattern classification. ICCAD Mingyu Woo, Seungwon Kim, Seokhyeong Kang
2016	J	`jnl`	Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC. ACM Trans. Design Autom. Electr. Syst. Seungwon Kim, Seokhyeong Kang, Ki Jin Han, Youngmin Kim
2016	C	`conf`	Novel approximate synthesis flow for energy-efficient FIR filter. ICCD Yesung Kang, Jaewoo Kim, Seokhyeong Kang
2016	—	`conf`	Skew control methodology for useful-skew implementation. ISOCC SangGi Do, Seungwon Kim, Seokhyeong Kang
2016	J	`jnl`	Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. ACM Trans. Design Autom. Electr. Syst. Sangmin Kim, Seokhyeong Kang, Youngsoo Shin
2016	J	`jnl`	Wakeup scheduling and its buffered tree synthesis for power gating circuits. Integr. Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin
2015	J	`jnl`	An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez
2015	C	`conf`	An optimal operating point by using error monitoring circuits with an error-resilient technique. VLSI-SoC Jaemin Lee, Seungwon Kim, Youngmin Kim, Seokhyeong Kang
2014	—	`conf`	A new methodology for reduced cost of resilience. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Seokhyeong Kang, Jiajia Li
2013	A	`conf`	Active-mode leakage reduction with data-retained power gating. DATE Andrew B. Kahng, Seokhyeong Kang, Bongil Park
2013	J	`jnl`	Enhancing the Efficiency of Energy-Constrained DVFS Designs. IEEE Trans. Very Large Scale Integr. Syst. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013	A	`conf`	High-performance gate sizing with a signoff timer. ICCAD Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar
2013	—	`conf`	Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani
2013	—	`—`	Low-Power Integrated-Circuit Implementation Exploiting System and Application Information / Seokhyeong Kang
2013	J	`jnl`	Many-Core Token-Based Adaptive Power Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong
2013	A*	`conf`	Smart non-default routing for clock power reduction. DAC Andrew B. Kahng, Seokhyeong Kang, Hyein Lee
2013	C	`conf`	Statistical analysis and modeling for error composition in approximate computation circuits. ICCD Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2012	A*	`conf`	Accuracy-configurable adder for approximate arithmetic designs. DAC Andrew B. Kahng, Seokhyeong Kang
2012	—	`conf`	Construction of realistic gate sizing benchmarks with known optimal solutions. ISPD Andrew B. Kahng, Seokhyeong Kang
2012	A	`conf`	MAPG: Memory access power gating. DATE Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong
2012	J	`jnl`	Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2012	A	`conf`	Sensitivity-guided metaheuristics for accurate discrete gate sizing. ICCAD Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov
2012	A	`conf`	TAP: token-based adaptive power gating. ISLPED Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong
2010	A*	`conf`	Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	A*	`conf`	Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	—	`conf`	Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	—	`conf`	Toward effective utilization of timing exceptions in design optimization. ISQED Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang