Senling Wang - RankMe

36 papers B 1C 1Journal 18Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Response-Nonlinearized DEMUX-TDC PUF for Resistance Against Modeling Attacks and Secure Authentication Protocols. IEEE Trans. Very Large Scale Integr. Syst. Tianming Ni, Hao Wu, Mu Nie, Aibin Yan, Senling Wang, Xiaoqing Wen, Jingchang Bian
2025	J	`jnl`	A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults. CoRR Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Ruijun Ma, Tianming Ni, Xiaoqing Wen, Hiroshi Takahashi
2025	J	`jnl`	A lightweight general PUF framework for resisting machine learning attacks. Integr. Tianming Ni, Fei Li, Zhengfeng Huang, Aibin Yan, Senling Wang, Xiaoqing Wen, Mu Nie, Jingchang Bian
2025	J	`jnl`	Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. IEEE Trans. Very Large Scale Integr. Syst. Ruijun Ma, Stefan Holst, Hui Xu, Xiaoqing Wen, Senling Wang, Jiuqi Li, Aibin Yan
2025	—	`conf`	LLM-Design Platform for Thermal-Failure-Aware 3D Chiplet Layout via Iterative Parameter Analysis. ATS Tai Song, Senling Wang, Xiaoqing Wen
2025	J	`jnl`	LOCO: A Low-Cost SNU-Self-Resilient Latch Using an Output-Split C-Element. CoRR Ruijun Ma, Xin Chen, Xiaoqing Wen, Hui Xu, Shengnan Ye, Chuanjian Zhang, Senling Wang
2025	J	`jnl`	SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices. J. Commun. Hisashi Okamoto, Shaoqi Wei, Senling Wang, Hiroshi Kai, Hiroshi Takahashi, Yoshinobu Higami, Akihiro Shimizu, Tianming Ni, Xiaoqing Wen
2025	—	`conf`	Software-Defined Secure Island for Testing Chiplet Systems. ATS Hisashi Okamoto, Senling Wang, Hiroshi Kai, Hiroyuki Yotsuyanagi, Yoshinobu Higami, Tianming Ni, Tai Song, Hiroshi Takahashi, Xiaoqing Wen
2024	J	`jnl`	A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers. ACM Trans. Design Autom. Electr. Syst. Qingsong Peng, Jingchang Bian, Zhengfeng Huang, Senling Wang, Aibin Yan
2024	J	`jnl`	A demultiplexer-based dual-path switching true random number generator. Microelectron. J. Tianming Ni, Kejie Xu, Hao Wu, Senling Wang, Mu Nie
2024	—	`conf`	Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. ITC-Asia Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen
2024	J	`jnl`	Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device. IEICE Trans. Inf. Syst. Xihong Zhou, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi
2023	—	`conf`	A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges. AsianHOST Tianming Ni, Fei Li, Qingsong Peng, Senling Wang, Xiaoqing Wen
2023	J	`jnl`	Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness. IEEE Trans. Circuits Syst. I Regul. Pap. Tianming Ni, Qingsong Peng, Jingchang Bian, Liang Yao, Zhengfeng Huang, Aibin Yan, Senling Wang, Xiaoqing Wen
2023	—	`conf`	Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning. ATS Mu Nie, Wen Jiang, Wankou Yang, Senling Wang, Xiaoqing Wen, Tianming Ni
2023	C	`conf`	QR-Code with Superimposed Text. APNOMS Naoya Tahara, Senling Wang, Hiroshi Kai, Hiroshi Takahashi, Masakatu Morii
2023	—	`conf`	SASL-JTAG: A Light-Weight Dependable JTAG. DFT Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni
2023	J	`jnl`	Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2022	—	`conf`	Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation. GCCE Tsutomu Inamoto, Tomoki Nishino, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi
2020	J	`jnl`	A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
2020	J	`jnl`	FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2018	J	`jnl`	Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
2018	—	`conf`	Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2018	B	`conf`	Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
2018	—	`conf`	On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara
2017	J	`jnl`	A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. IEICE Trans. Inf. Syst. Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2017	—	`conf`	Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD). ATS Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi
2016	—	`conf`	A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
2016	J	`jnl`	Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. IPSJ Trans. Syst. LSI Des. Methodol. Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2016	—	`conf`	Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
2015	—	`conf`	Diagnosis of Delay Faults Considering Hazards. ISVLSI Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2015	J	`jnl`	Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi
2013	J	`jnl`	Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase
2012	—	`conf`	A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara
2012	—	`conf`	Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara
2011	—	`conf`	Genetic algorithm based approach for segmented testing. DSN Workshops Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato