Seng-Pan U - RankMe

90 papers C 5Journal 34Unranked 51

Year	Rank	Type	Title / Venue / Authors
2021	C	`conf`	A 2.52 μΑ Wearable Single Lead Ternary Neural Network Based Cardiac Arrhythmia Detection Processor. ISCAS Syed Muhammad Abubakar, Yue Yin, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia
2021	J	`jnl`	A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device. IEEE Trans. Biomed. Circuits Syst. Yue Yin, Syed Muhammad Abubakar, Songyao Tan, Jiahua Shi, Peilin Yang, Wendi Yang, Hanjun Jiang, Zhihua Wang, Wen Jia, Seng-Pan U
2020	—	`conf`	A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift. A-SSCC Yue Yin, Syed Muhammad Abubakar, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia
2019	—	`conf`	A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. A-SSCC Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2019	J	`jnl`	A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. IEEE J. Solid State Circuits Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2019	—	`conf`	A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. A-SSCC Junhao Liang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, Hanjun Jiang
2019	J	`jnl`	Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2019	J	`jnl`	Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Dezhi Xing, Yan Zhu, Chi-Hang Chan, Franco Maloberti, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U
2018	—	`conf`	A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. VLSI Circuits Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2018	—	`conf`	A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems. VLSI-DAT Fangyu Mao, Yan Lu, Seng-Pan U, Rui Paulo Martins
2018	—	`conf`	A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. A-SSCC Wenning Jiang, Yan Zhu, Chi-Hang Chan, Boris Murmann, Seng-Pan U, Rui Paulo Martins
2018	C	`conf`	A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT. ISCAS Fangyu Mao, Yan Lu, Jie Lin, Chenchang Zhan, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits Chi-Hang Chan, Yan Zhu, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
2018	—	`conf`	A dual-output SC converter with dynamic power allocation for multicore application processors. ASP-DAC Junmin Jiang, Yan Lu, Xun Liu, Wing-Hung Ki, Philip K. T. Mok, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator. IEEE J. Solid State Circuits Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaofeng Yang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. IEEE Trans. Very Large Scale Integr. Syst. Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	Passive Noise Shaping in SAR ADC With Improved Efficiency. IEEE Trans. Very Large Scale Integr. Syst. Yan Song, Chi-Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	Quick and cost-efficient A/D converter static characterization using low-precision testing signal. Microelectron. J. Wei Wei Qin, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. ISSCC Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. ISSCC Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS. ISSCC Junmin Jiang, Yan Lu, Wing-Hung Ki, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency. ISSCC Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. IEEE J. Solid State Circuits Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. IEEE Trans. Very Large Scale Integr. Syst. Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	A 12b 180MS/s 0.068mm IEEE Trans. Circuits Syst. I Regul. Pap. Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2017	—	`conf`	A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. A-SSCC U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2017	—	`conf`	A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. A-SSCC Wei Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2017	J	`jnl`	A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. ISIE Xia Du, Chi-Seng Lam, Sai-Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. ESSCIRC Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	A sub-1V 78-nA bandgap reference with curvature compensation. Microelectron. J. Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2017	C	`conf`	CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. IECON Chi-Wa U, Chi-Seng Lam, Man-Kay Law, Sai-Weng Sin, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. ISSCC Kostas Doris, David Robertson, Seung-Tak Ryu, Seng-Pan U
2017	J	`jnl`	Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A 0.011mm A-SSCC Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration. A-SSCC Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U
2016	—	`conf`	A 12b 180MS/s 0.068mm ESSCIRC Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	J	`jnl`	A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. ISIC Wei Li, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	J	`jnl`	A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. IEEE Trans. Circuits Syst. II Express Briefs Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A digital LDO with transient enhancement and limit cycle oscillation reduction. APCCAS Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. A-SSCC Yuan Ren, Sai-Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
2016	J	`jnl`	An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. IEEE J. Solid State Circuits Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
2016	J	`jnl`	Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. Yan Zhu, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins
2016	J	`jnl`	Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Wing-Hung Ki
2016	J	`jnl`	Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2015	—	`conf`	20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. ISSCC Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2015	—	`conf`	26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2015	—	`conf`	A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2015	J	`jnl`	Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2014	—	`conf`	An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. ESSCIRC Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
2014	C	`conf`	Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. ISCAS Da Feng, Franco Maloberti, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2014	J	`jnl`	Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2013	J	`jnl`	A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. IEEE J. Solid State Circuits Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2013	J	`jnl`	A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2013	—	`conf`	A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. MWSCAS Li Ding, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. APCCAS Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. APCCAS Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. APCCAS Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	An ELD tracking compensation technique for active-RC CT ΣΔ modulators. MWSCAS Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2011	—	`conf`	A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. A-SSCC Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2011	—	`conf`	A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2011	—	`conf`	A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2011	—	`conf`	Hybrid loopfilter sigma-delta modulator with NTF zero compensation. ISOCC Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2010	J	`jnl`	1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. IET Circuits Devices Syst. Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2010	—	`conf`	A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. APCCAS Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2010	—	`conf`	An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2008	—	`conf`	A 1-V 90dB DR audio stereo DAC with embedding headphone driver. APCCAS Kim-Fai Wong, Ka-Ian Lei, Seng-Pan U, Rui Paulo da Silva Martins
2008	—	`conf`	A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller. APCCAS Ngai Kong, Seng-Pan U, Rui Paulo Martins
2008	—	`conf`	A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2008	—	`conf`	A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. APCCAS Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2008	—	`conf`	A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2007	J	`jnl`	Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers. IET Circuits Devices Syst. Pui-In Mak, Seng-Pan U, Rui Paulo Martins
2005	—	`conf`	A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS. CICC Pui-In Mak, Seng-Pan U, Rui Paulo Martins
2005	J	`jnl`	Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends. IEEE Trans. Circuits Syst. I Regul. Pap. Pui-In Mak, Seng-Pan U, Rui Paulo Martins
2004	J	`jnl`	A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS. IEEE J. Solid State Circuits Seng-Pan U, Rui Paulo Martins, José E. Franca
2003	—	`conf`	A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement. ICECS Pui-In Mak, Seng-Pan U, Rui Paulo Martins
2003	—	`conf`	A very area/power efficient mixed signal circuit for voice signal processing in 0.18 digital technology. ESSCIRC João Risques, Jorge Duarte, Vasco Amaro, Seng-Pan U, Kuok Vai Chiang, Ka Fai Chang, Keng Chong Lai
2003	—	`conf`	Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver. ICECS Pui-In Mak, Chi-sam Sou, Seng-Pan U, Rui Paulo Martins
2003	—	`conf`	Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. ICASSP (6) Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2002	—	`conf`	N-path multirate sigma-delta modulator for high-frequency applications. ICECS Fan Lou, Seng-Pan U, Rui Paulo Martins
2000	C	`conf`	A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction. ISCAS Seng-Pan U, Rui Paulo Martins, José E. Franca
1998	—	`conf`	A novel half-band SC architecture for efficient analog impulse sampled interpolation. ICECS Seng-Pan U, Rui Paulo Martins, José E. Franca