Seng-Pan U. - RankMe

49 papers C 11Journal 10Unranked 28

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency. ISSCC Fangyu Mao, Yan Lu, Seng-Pan U., Rui Paulo Martins
2013	C	`conf`	A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2013	C	`conf`	A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. ISCAS Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2012	—	`conf`	A 0.024 mm ESSCIRC Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
2012	C	`conf`	A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. ISCAS Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2012	—	`conf`	A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. ESSCIRC Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
2012	—	`conf`	A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. CICC Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2012	J	`jnl`	A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2012	J	`jnl`	An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2011	—	`conf`	A 0.024mm ISSCC He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2011	—	`conf`	A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	J	`jnl`	A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2010	—	`conf`	A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. ICECS Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	J	`jnl`	A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	C	`conf`	A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	—	`conf`	An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. APCCAS Li Ding, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	—	`conf`	An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang
2010	J	`jnl`	Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. Circuits Syst. II Express Briefs U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2010	J	`jnl`	Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	C	`conf`	A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	—	`conf`	A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	J	`jnl`	Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. IEEE Trans. Circuits Syst. I Regul. Pap. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	J	`jnl`	On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Pui-In Mak, Seng-Pan U., Rui Paulo Martins
2008	J	`jnl`	Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. IEEE Trans. Circuits Syst. II Express Briefs Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins
2007	C	`conf`	A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. ISCAS Weng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
2006	—	`conf`	A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. APCCAS Ka-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins
2006	C	`conf`	A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy. ISCAS Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins
2006	C	`conf`	A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator. ISCAS Chon-In Lao, Seng-Pan U., Rui Paulo Martins
2006	C	`conf`	A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. ISCAS Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2006	C	`conf`	A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. ISCAS Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2006	C	`conf`	Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. ISCAS Pui-In Mak, Seng-Pan U., Rui Paulo Martins
2005	—	`conf`	A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. ISCAS (1) Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
2005	—	`conf`	A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. ISCAS (2) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2005	—	`conf`	A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. ISCAS (4) Chon-In Lao, Seng-Pan U., Rui Paulo Martins
2005	—	`conf`	A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. ISCAS (2) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2005	—	`conf`	A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. ISCAS (4) Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins
2004	—	`conf`	A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems. ISCAS (5) Pui-In Mak, Man-Chung Wong, Seng-Pan U.
2004	—	`conf`	A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. ISCAS (1) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2004	—	`conf`	A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. ISCAS (4) Pui-In Mak, Seng-Pan U., Rui Paulo Martins
2004	—	`conf`	An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. ISCAS (1) Pui-In Mak, Kin-Kwan Ma, Weng-leng Mok, Chi-sam Sou, Kit-man Ho, Cheng-Man Ng, Seng-Pan U., Rui Paulo Martins
2004	J	`jnl`	Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. IEEE Trans. Instrum. Meas. Seng-Pan U., Sai-Weng Sin, Rui Paulo Martins
2003	—	`conf`	A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. ISCAS (1) Chon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins
2003	—	`conf`	Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. ISCAS (1) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca
2002	—	`conf`	Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. ISCAS (4) Seng-Pan U., Rui Paulo Martins, José E. Franca
2001	—	`conf`	A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. ISCAS (1) Seng-Pan U., Rui Paulo Martins, José E. Franca
2001	—	`conf`	High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. ISCAS (1) Seng-Pan U., Rui Paulo Martins, José E. Franca
1999	—	`conf`	High performance multirate SC circuits with predictive correlated double sampling technique. ISCAS (2) Seng-Pan U., Rui Paulo Martins, José E. Franca
1999	—	`conf`	Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. ISCAS (2) Seng-Pan U., Rui Paulo Martins, José E. Franca
1996	—	`conf`	New impulse sampled IIR switched-capacitor interpolators. ICECS Seng-Pan U., Rui Paulo Martins, José E. Franca