Seiyang Yang

11 papers A* 1A 4Misc 1Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2014 A conf
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy.
DATE
Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, DaeSeo Cha, Junhyuck Park, Jay Kim
2013 J jnl
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
2011 A conf
A new distributed event-driven gate-level HDL simulation by accurate prediction.
DATE
Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
2011 A conf
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models.
DATE
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
2008 — conf
A fast two-pass HDL simulation with on-demand dump.
ASP-DAC
Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang
2008 Misc conf
Simulation Acceleration with HW Re-Compilation Avoidance.
VLSI Design
Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang
2008 — conf
Temporal parallel gate-level timing simulation.
HLDVT
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
2004 A* conf
A new state assignment technique for testing and low power.
DAC
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski
1992 J jnl
PLADE: a two-stage PLA decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Maciej J. Ciesielski, Seiyang Yang
1991 J jnl
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seiyang Yang, Maciej J. Ciesielski
1989 A conf
PLA decomposition with generalized decoders.
ICCAD
Seiyang Yang, Maciej J. Ciesielski