Seiya Kasai

18 papers Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2021 — conf
Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim.
FPT
Ying Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, Seiya Kasai
2018 — conf
Amoeba-Inspired Electronic Solution-Searching System and Its Application to Finding Walking Maneuver of a Multi-legged Robot.
ISMVL
Kenta Saito, Naoki Suefuji, Seiya Kasai, Masashi Aono
2018 J jnl
Amoeba-inspired Electronic Computing System and its Application to Autonomous Walking of a Multi-legged Robot.
FLAP
Kenta Saito, Naoki Suefuji, Seiya Kasai, Masashi Aono
2017 J jnl
Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network.
Int. J. Parallel Emergent Distributed Syst.
Ryota Kuroda, Seiya Kasai
2016 J jnl
Design Framework of Image Sensor System Based on Dynamic Range Extension by Adding Noise for Saturated Conditions.
IEEE Trans. Syst. Man Cybern. Syst.
Yukihiro Tadokoro, Seiya Kasai, Akihisa Ichiki, Hiroya Tanaka
2015 J jnl
Analysis on Non-Ideal Nonlinear Characteristics of Graphene-Based Three-Branch Nano-Junction Device.
IEICE Trans. Electron.
Xiang Yin, Masaki Sato, Seiya Kasai
2015 J jnl
Concept, analysis, and demonstration of a novel delay network exhibiting stochastic resonance induced by external noise.
Digit. Signal Process.
Yukihiro Tadokoro, Seiya Kasai, Akihisa Ichiki
2013 — book
Introduction to Noise-Resilient Computing
Svetlana N. Yanushkevich, Seiya Kasai, Golam Tangim
2013 — conf
Noise-Tolerant Model of a Ternary Inverter Based on Markov Random Field.
ISMVL
Golam Tangim, Svetlana N. Yanushkevich, Seiya Kasai, Vlad P. Shmerko
2009 J jnl
Investigation on Stochastic Resonance in Quantum Dot and Its Summing Network.
Int. J. Nanotechnol. Mol. Comput.
Seiya Kasai
2009 — conf
Multi-path Switching Device Utilizing a Multi-terminal Nanowire Junction for MDD-Based Logic Circuit.
ISMVL
Seiya Kasai, Yuta Shiratori, Kensuke Miura, Nan-Jian Wu
2009 — conf
Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors.
ISMVL
Wancheng Zhang, Nan-Jian Wu, Tamotsu Hashizume, Seiya Kasai
2008 J jnl
Fabrication and Characterization of Active and Sequential Circuits Utilizing Schottky-Wrap-Gate-Controlled GaAs Hexagonal Nanowire Network Structures.
IEICE Trans. Electron.
Hong-Quan Zhao, Seiya Kasai, Tamotsu Hashizume, Nan-Jian Wu
2007 J jnl
Integration of interdigital-gated plasma wave device for proximity communication system application.
Microelectron. J.
Abdul Manaf Hashim, Seiya Kasai, Tamotsu Hashizume, Hideki Hasegawa
2007 J jnl
Multiple Path Switching Device Utilizing Size-Controlled Nano-Schottky Wrap Gates for MDD-Based Logic Circuits.
J. Multiple Valued Log. Soft Comput.
Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori
2007 J jnl
Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier.
Microelectron. J.
Abdul Manaf Hashim, Seiya Kasai, Kouichi Iizuka, Tamotsu Hashizume, Hideki Hasegawa
2006 J jnl
Future of Heterostructure Microelectronics and Roles of Materials Research for Its Progress.
IEICE Trans. Electron.
Hideki Hasegawa, Seiya Kasai, Taketomo Sato, Tamotsu Hashizume
2005 — conf
III-V Compound Semiconductor Nanotechnology for Smart Systems.
ICMENS
Hideki Hasegawa, Seiya Kasai