Seiji Mochizuki

19 papers B 1Misc 1Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2025 Misc conf
20-µs Low-latency Simple Video Coding with High Compression Ratio for IoT Video-transmission.
ICNC
Mai Yamakawa, Seiji Mochizuki, Yu Kuwahara, Tsuyoshi Kato, Kousuke Imamura, Tetsuya Matsumura
2023 — conf
CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images.
IoTaIS
Yusei Horikawa, Seiji Mochizuki, Kousuke Imamura, Tetsuya Matsumura
2023 — conf
Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System.
GCCE
Yusei Horikawa, Renpei Yoshida, Seiji Mochizuki, Tetsuya Matsumura
2023 — conf
Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video.
GCCE
Mai Yamaguchi, Mai Yamakawa, Seiji Mochizuki, Kousuke Imamura, Toshiki Kanamoto, Tetsuya Matsumura
2022 J jnl
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control.
IEEE J. Solid State Circuits
Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei
2021 — conf
4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control.
ISSCC
Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei
2019 — conf
Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis.
ISPACS
Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki
2018 — conf
Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices.
IOTAIS
Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura
2017 J jnl
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori
2016 — conf
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems.
ISSCC
Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori
2016 — conf
71% Reducing the memory bandwidth requirement for a multi-standard video codec by lossless compression of video using a combination of 2D-DPCM and Variable Length Coding.
ICICDT
Chi Lan Phuong Nguyen, My Phi Ngoc Nguyen, Hung Van Cao, Katsushige Matsubara, Keisuke Matsumoto, Seiji Mochizuki, Kenichi Iwata
2012 B conf
Intra texture prediction based on repetitive pixel replenishment.
ICIP
Kenichi Iwata, Ryoji Hashimoto, Seiji Mochizuki, Kiyoharu Aizawa
2011 — conf
A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder.
ASICON
Tuan Minh Phan Ho, Thang Minh Le, Khanh Duy Vu, Seiji Mochizuki, Kenichi Iwata, Keisuke Matsumoto, Hiroshi Ueda
2010 J jnl
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits.
IEEE J. Solid State Circuits
Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori
2009 J jnl
A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS.
IEEE J. Solid State Circuits
Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe
2009 — conf
A 342mW mobile application processor with full-HD multi-standard video codec.
ISSCC
Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori
2009 J jnl
A Full HD Multistandard Video Codec for Mobile Applications.
IEEE Micro
Motoki Kimura, Kenichi Iwata, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Hiromi Watanabe
2009 — conf
Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture.
ASP-DAC
Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori
2008 J jnl
A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS.
IEEE J. Solid State Circuits
Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe