Seiji Kajihara

161 papers A* 3A 21B 5C 10Misc 16Journal 52Unranked 54

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Area Efficient 0.009-mm IEEE Trans. Very Large Scale Integr. Syst. Joshua Adiel Wijaya, Poki Chen, Lucky Kumar Pradhan, Ahmad Shahid Bhatti, Seiji Kajihara
2022	J	`jnl`	A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection. IEEE Access Poki Chen, Joshua Adiel Wijaya, Seiji Kajihara, Trio Adiono, Hsiang-Yu Chen, Ruei-Ting Wang, Yousuke Miyake
2022	A	`conf`	A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications. ITC Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara
2022	—	`conf`	Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. ITC-Asia Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
2022	—	`conf`	On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and Prediction. ATS Takaaki Kato, Yousuke Miyake, Seiji Kajihara
2021	J	`jnl`	On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. IEICE Trans. Inf. Syst. Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian
2020	J	`jnl`	A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
2020	J	`jnl`	High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters. IEEE Trans. Very Large Scale Integr. Syst. Poki Chen, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui, John Carl Joel Salao Marquez, Seiji Kajihara, Yousuke Miyake
2020	Misc	`conf`	Innovative Test Practices in Asia. VTS Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama
2020	—	`conf`	On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor. ATS Masayuki Gondo, Yousuke Miyake, Takaaki Kato, Seiji Kajihara
2020	C	`conf`	On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. IOLTS Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura
2020	—	`conf`	Path Delay Measurement with Correction for Temperature And Voltage Variations. ITC-Asia Yousuke Miyake, Takaaki Kato, Seiji Kajihara
2019	—	`conf`	A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. ITC-Asia Yousuke Miyake, Yasuo Sato, Seiji Kajihara
2019	—	`conf`	A Static Method for Analyzing Hotspot Distribution on the LSI. ITC-Asia Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
2019	—	`conf`	FPGA implementation of ECDSA for Blockchain. ICCE-TW Shoi Tachibana, Shunsuke Araki, Seiji Kajihara, Shigeyuki Azuchi, Yukishige Nakajo, Hideki Shoda
2019	C	`conf`	On-Chip Delay Measurement for In-Field Test of FPGAs. PRDC Yousuke Miyake, Yasuo Sato, Seiji Kajihara
2019	—	`conf`	On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs. ITC-Asia Yousuke Miyake, Seiji Kajihara, Poki Chen
2018	—	`conf`	Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. ATS Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian
2018	—	`conf`	Good Die Prediction Modelling from Limited Test Items. ITC-Asia Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura
2018	—	`conf`	On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara
2017	A	`conf`	Analysis and mitigation or IR-Drop induced scan shift-errors. ITC Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
2017	—	`conf`	On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. ITC-Asia Yousuke Miyake, Yasuo Sato, Seiji Kajihara
2017	—	`conf`	Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. ATS Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian
2016	—	`conf`	A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
2016	J	`jnl`	Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara
2016	J	`jnl`	Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
2016	—	`conf`	Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. ATS Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte
2015	B	`conf`	Identification of high power consuming areas with gate type and logic level information. ETS Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2015	—	`conf`	Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian
2015	J	`jnl`	Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi
2014	—	`conf`	An On-Chip Digital Environment Monitor for Field Test. ATS Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura
2014	—	`conf`	Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories. ATS Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara
2014	J	`jnl`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2014	C	`conf`	Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA. PRDC Yasuo Sato, Masafumi Monden, Yousuke Miyake, Seiji Kajihara
2014	—	`conf`	Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
2013	J	`jnl`	A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing. IEICE Trans. Inf. Syst. Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
2013	—	`conf`	A Stochastic Model for NBTI-Induced LSI Degradation in Field. Asian Test Symposium Yasuo Sato, Seiji Kajihara
2013	J	`jnl`	LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte
2013	—	`conf`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2013	Misc	`conf`	On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
2013	J	`jnl`	Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase
2013	—	`conf`	Search Space Reduction for Low-Power Test Generation. Asian Test Symposium Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2012	J	`jnl`	A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2012	—	`conf`	A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara
2012	Misc	`conf`	A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara
2012	A	`conf`	DART: Dependable VLSI test architecture and its implementation. ITC Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
2012	—	`conf`	Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara
2012	A	`conf`	On pinpoint capture power management in at-speed scan test generation. ITC Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2012	B	`conf`	On-chip temperature and voltage measurement for field testing. ETS Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara
2011	J	`jnl`	A GA-Based IEICE Trans. Inf. Syst. Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
2011	A	`conf`	A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang
2011	J	`jnl`	Delay Testing: Improving Test Quality and Avoiding Over-testing. Inf. Media Technol. Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
2011	J	`jnl`	Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
2011	J	`jnl`	Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2011	—	`conf`	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
2011	—	`conf`	Genetic algorithm based approach for segmented testing. DSN Workshops Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato
2011	—	`conf`	Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. Asian Test Symposium Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara
2011	Misc	`conf`	Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor
2011	A	`conf`	SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich
2011	A	`conf`	Transition-Time-Relation based capture-safety checking for at-speed scan test generation. DATE Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
2010	J	`jnl`	A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2010	C	`conf`	Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2010	J	`jnl`	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
2010	J	`jnl`	On Delay Test Quality for Test Cubes. Inf. Media Technol. Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
2010	J	`jnl`	On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
2010	B	`conf`	On estimation of NBTI-Induced delay degradation. ETS Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
2009	C	`conf`	A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. PRDC Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
2009	A	`conf`	A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
2009	—	`conf`	CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa
2008	B	`conf`	A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2008	J	`jnl`	A Novel Per-Test Fault Diagnosis Method Based on the Extended IEICE Trans. Inf. Syst. Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara
2008	—	`conf`	CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
2008	C	`conf`	Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
2008	A	`conf`	Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2008	J	`jnl`	Estimation of Delay Test Quality and Its Application to Test Generation. Inf. Media Technol. Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2008	J	`jnl`	Estimation of Delay Test Quality and Its Application to Test Generation. IPSJ Trans. Syst. LSI Des. Methodol. Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2008	J	`jnl`	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2008	J	`jnl`	On Detection of Bridge Defects with Stuck-at Tests. IEICE Trans. Inf. Syst. Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy
2008	J	`jnl`	Special Section on Test and Verification of VLSIs. IEICE Trans. Inf. Syst. Seiji Kajihara, Michiko Inoue
2007	J	`jnl`	A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2007	A	`conf`	A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
2007	A*	`conf`	Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
2007	A	`conf`	Estimation of delay test quality and its application to test generation. ICCAD Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2006	A	`conf`	A Framework of High-quality Transition Fault ATPG for Scan Circuits. ITC Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006	Misc	`conf`	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
2006	J	`jnl`	A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2006	J	`jnl`	A Per-Test Fault Diagnosis Method Based on the IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2006	J	`jnl`	A Statistical Quality Model for Delay Testing. IEICE Trans. Electron. Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
2006	—	`conf`	A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006	C	`conf`	Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
2006	J	`jnl`	On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Trans. Inf. Syst. Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu
2005	Misc	`conf`	Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. VLSI Design Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan
2005	J	`jnl`	Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
2005	—	`conf`	Evaluation of the statistical delay quality model. ASP-DAC Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
2005	A	`conf`	Invisible delay quality - SDQM model lights up what could not be seen. ITC Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara
2005	A	`conf`	Low-capture-power test generation for scan-based at-speed testing. ITC Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005	J	`jnl`	On Design for I IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
2005	—	`conf`	On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy
2005	Misc	`conf`	On Low-Capture-Power Test Generation for Scan Testing. VTS Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005	J	`jnl`	On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis. IEICE Trans. Inf. Syst. Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka
2005	A*	`conf`	Path delay test compaction with process variation tolerance. DAC Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2005	—	`conf`	Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. ASP-DAC Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
2005	J	`jnl`	Test cost reduction for logic circuits: Reduction of test data volume and test application time. Syst. Comput. Jpn. Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
2004	J	`jnl`	Don't Care Identification and Statistical Encoding for Test Data Compression. IEICE Trans. Inf. Syst. Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
2004	B	`conf`	Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. ETS Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy
2004	—	`conf`	Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
2004	A	`conf`	On per-test fault diagnosis using the X-fault model. ICCAD Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2004	Misc	`conf`	Random Access Scan: A solution to test power, test data volume and test time. VLSI Design Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
2004	—	`conf`	Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu
2004	J	`jnl`	XID: Don't care identification of test patterns for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kohei Miyase, Seiji Kajihara
2003	C	`conf`	A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
2003	J	`jnl`	BIST-oriented test pattern generator for detection of transition faults. Syst. Comput. Jpn. Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara
2003	J	`jnl`	Evaluation of Delay Testing Based on Path Selection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yoshimura
2003	C	`conf`	On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. ICCD Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty
2003	—	`conf`	On Estimation of Fault Efficiency for Path Delay Faults. Asian Test Symposium Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka
2003	J	`jnl`	On Selecting Testable Paths in Scan Designs. J. Electron. Test. Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
2003	—	`conf`	On effective criterion of path selection for delay testing. ASP-DAC Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura
2003	J	`jnl`	On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
2003	—	`conf`	Optimal Scan Tree Construction with Test Vector Modification for Test Compression. Asian Test Symposium Kohei Miyase, Seiji Kajihara
2002	—	`conf`	A Method of Static Test Compaction Based on Don't Care Identification. DELTA Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
2002	C	`conf`	Don't-Care Identification on Specific Bits of Test Patterns. ICCD Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy
2002	Misc	`conf`	On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
2002	A	`conf`	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
2002	—	`conf`	On selecting testable paths in scan designs. ETW Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
2002	—	`conf`	Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy
2002	—	`conf`	Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
2002	Misc	`conf`	Test Vector Modification for Power Reduction during Scan Testing. VTS Seiji Kajihara, Koji Ishida, Kohei Miyase
2001	—	`conf`	An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz
2001	—	`conf`	Hybrid BIST Using Partially Rotational Scan. Asian Test Symposium Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara
2001	A	`conf`	On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. ICCAD Seiji Kajihara, Kohei Miyase
2000	—	`conf`	Enhanced untestable path analysis using edge graphs. Asian Test Symposium Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy
2000	A	`conf`	On validating data hold times for flip-flops in sequential circuits. ITC Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
2000	A	`conf`	Selection of potentially testable path delay faults for test generation. ITC Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
1999	—	`conf`	On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. Asian Test Symposium Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko
1999	—	`conf`	On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
1999	—	`conf`	On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
1998	—	`conf`	An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita
1998	Misc	`conf`	On Test Pattern Compaction Using Random Pattern Fault Simulation. VLSI Design Seiji Kajihara, Kewal K. Saluja
1997	Misc	`conf`	A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	A diagnosis method for single logic design errors in gate-level combinational circuits. Syst. Comput. Jpn. Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita
1997	J	`jnl`	Compact test sets for high defect coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
1997	J	`jnl`	On invariant implication relations for removing partial circuits. Syst. Comput. Jpn. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
1997	—	`conf`	On the Adders with Minimum Tests. Asian Test Symposium Seiji Kajihara, Tsutomu Sasao
1997	J	`jnl`	Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electron. Test. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1996	Misc	`conf`	On the effects of test compaction on defect coverage. VTS Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
1996	—	`conf`	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1995	J	`jnl`	Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis. IEICE Trans. Inf. Syst. Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita
1995	Misc	`conf`	Compact test generation for bridging faults under I VTS Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara
1995	J	`jnl`	Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1995	J	`jnl`	Partial scan design and test sequence generation based on reduced scan shift method. J. Electron. Test. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1995	Misc	`conf`	Resynthesis for sequential circuits designed with a specified initial state. VTS Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995	J	`jnl`	Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. IEICE Trans. Inf. Syst. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995	—	`conf`	Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995	—	`conf`	Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1994	Misc	`conf`	On compacting test sets by addition and removal of test vectors. VTS Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1994	A	`conf`	Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1993	A*	`conf`	Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1993	J	`jnl`	Removal of redundancy in combinational circuits under classification of undetectable faults. Syst. Comput. Jpn. Seiji Kajihara, Kozo Kinoshita, Haruko Shiba
1993	A	`conf`	Test generation for multiple faults based on parallel vector pair analysis. ICCAD Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita
1992	—	`conf`	Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. FTCS Seiji Kajihara, Haruko Shiba, Kozo Kinoshita
1991	J	`jnl`	Stuck-open faults test generation for cmos combinational circuits. Syst. Comput. Jpn. Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita