Sehyeon Chung

14 papers A* 1A 7C 1Journal 2Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Enhancing Pin Accessibility Through Pin Pattern Migration and Optimization Across Cell Boundaries. ASP-DAC Hyunbae Seo, Sehyeon Chung, Taewhan Kim
2026	—	`conf`	ML-driven Design Technology Co-Optimization Framework for Advanced Technology Nodes. ASP-DAC Hyunbae Seo, Handong Cho, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim
2026	J	`jnl`	Utilization of standard cells with hybrid-threshold-voltage for timing and power optimization. Integr. Sehyeon Chung, Taewhan Kim
2025	A	`conf`	Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing. ICCAD Jaehoon Ahn, Sehyeon Chung, Taewhan Kim
2025	A*	`conf`	Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery. DAC Sehyeon Chung, Hyun-chul Hwang, Byung Su Kim, Jaeha Lee, Kunhyuk Kang, Taewhan Kim
2025	A	`conf`	Synthesis of Standard Cells of Minimum Delay. ICCAD Sehyeon Chung, Hyunbae Seo, Taewhan Kim
2025	C	`conf`	Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques. ICCD Yeongyeong Shin, Sehyeon Chung, Taewhan Kim
2024	A	`conf`	Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. ICCAD Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim
2024	A	`conf`	Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. DATE Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim
2023	A	`conf`	Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. DATE Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim
2022	J	`jnl`	ECO routing based on network flow method. Integr. Sehyeon Chung, Taewhan Kim
2022	A	`conf`	Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. ISLPED Sehyeon Chung, Jooyeon Jeong, Taewhan Kim
2022	A	`conf`	Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. ISLPED Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park
2021	—	`conf`	Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. ISOCC Jaejoon Yoon, Sehyeon Chung, Taewhan Kim