Seetal Potluri

42 papers A 7B 2C 4Journal 21Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
CoupledNets: Resisting Feature Snooping Attacks on Neural Processing Units through Noise Injection into Models.
IACR Cryptol. ePrint Arch.
Sachintha Kavishan Jayarathne, Seetal Potluri
2024 J jnl
SoK: Model Reverse Engineering Threats for Neural Network Hardware.
IACR Cryptol. ePrint Arch.
Seetal Potluri, Farinaz Koushanfar
2023 A conf
Scalable Scan-Chain-Based Extraction of Neural Network Models.
DATE
Shui Jiang, Seetal Potluri, Tsung-Yi Ho
2023 J jnl
SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu
2022 — conf
PR Crisis: Analyzing and Fixing Partial Reconfiguration in Multi-Tenant Cloud FPGAs.
ASHES@CCS
Emre Karabulut, Chandu Yuvarajappa, Mohammed Iliyas Shaik, Seetal Potluri, Amro Awad, Aydin Aysu
2022 A conf
RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library.
DATE
Furkan Aydin, Emre Karabulut, Seetal Potluri, Erdem Alkim, Aydin Aysu
2022 J jnl
RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library.
IACR Cryptol. ePrint Arch.
Furkan Aydin, Emre Karabulut, Seetal Potluri, Erdem Alkim, Aydin Aysu
2022 C conf
Towards AI-Enabled Hardware Security: Challenges and Opportunities.
IOLTS
Hossein Sayadi, Mehrdad Aliasgari, Furkan Aydin, Seetal Potluri, Aydin Aysu, Jack Edmonds, Sara Tehranipoor
2021 J jnl
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Priyank Kashyap, Furkan Aydin, Seetal Potluri, Paul D. Franzon, Aydin Aysu
2021 J jnl
SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation.
IACR Cryptol. ePrint Arch.
Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu
2021 A conf
Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware.
ICCAD
Seetal Potluri, Aydin Aysu
2021 J jnl
Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware.
IACR Cryptol. ePrint Arch.
Seetal Potluri, Aydin Aysu
2021 — conf
iTimed: Cache Attacks on the Apple A10 Fusion SoC.
HOST
Gregor Haas, Seetal Potluri, Aydin Aysu
2021 J jnl
iTimed: Cache Attacks on the Apple A10 Fusion SoC.
IACR Cryptol. ePrint Arch.
Gregor Haas, Seetal Potluri, Aydin Aysu
2020 — conf
DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks.
SAMOS
Furkan Aydin, Priyank Kashyap, Seetal Potluri, Paul D. Franzon, Aydin Aysu
2020 J jnl
Efficacy of Satisfiability Based Attacks in the Presence of Circuit Reverse Engineering Errors.
CoRR
Qinhan Tan, Seetal Potluri, Aydin Aysu
2020 C conf
Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors.
ISCAS
Qinhan Tan, Seetal Potluri, Aydin Aysu
2020 — conf
FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips.
NEWCAS
Huili Chen, Seetal Potluri, Farinaz Koushanfar
2020 A conf
Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.
ICCAD
Francesco Regazzoni, Shivam Bhasin, Amir Alipour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, Vincent Beroulle, Giorgio Di Natale, Paul D. Franzon, David Hély, Naofumi Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, Ilia Polian, Seetal Potluri, Rei Ueno, Elena-Ioana Vatajelu, Ville Yli-Mäyry
2020 J jnl
Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips.
IET Comput. Digit. Tech.
Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri
2020 J jnl
Security of Microfluidic Biochip: Practical Attacks and Countermeasures.
ACM Trans. Design Autom. Electr. Syst.
Huili Chen, Seetal Potluri, Farinaz Koushanfar
2020 — conf
SeqL: Secure Scan-Locking for IP Protection.
ISQED
Seetal Potluri, Aydin Aysu, Akash Kumar
2020 J jnl
SeqL: Secure Scan-Locking for IP Protection.
CoRR
Seetal Potluri, Aydin Aysu, Akash Kumar
2019 J jnl
Design-for-Testability of On-Chip Control in mVLSI Biochips.
IEEE Des. Test
Seetal Potluri, Paul Pop, Jan Madsen
2018 J jnl
MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis.
J. Low Power Electron.
Patanjali SLPSK, Milan Patnaik, Seetal Potluri, V. Kamakoti
2017 — conf
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips.
DFT
Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri
2017 C conf
BioChipWork: Reverse Engineering of Microfluidic Biochips.
ICCD
Huili Chen, Seetal Potluri, Farinaz Koushanfar
2017 — conf
Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs.
ATS
Seetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, Shahin Toutounchi
2017 J jnl
Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing.
ACM Trans. Design Autom. Electr. Syst.
Satya Trinadh Adireddy, Seetal Potluri, Ch. Sobhan Babu, Veezhinathan Kamakoti, Shiv Govind Singh
2017 A conf
Synthesis of on-chip control circuits for mVLSI biochips.
DATE
Seetal Potluri, Alexander Schneider, Martin Horslev-Petersen, Paul Pop, Jan Madsen
2016 A conf
Architecture synthesis for cost-constrained fault-tolerant flow-based biochips.
DATE
Morten Chabert Eskesen, Paul Pop, Seetal Potluri
2016 B conf
Component fault localization using switching current measurements.
ETS
Seetal Potluri, Satya Trinadh, Siddhant Saraf, Kamakoti Veezhinathan
2016 J jnl
Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures.
J. Low Power Electron.
Sanjay Burman, Seetal Potluri, Debdeep Mukhopadhyay, Kamakoti Veezhinathan
2015 J jnl
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing.
ACM Trans. Design Autom. Electr. Syst.
Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan
2015 A conf
DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests.
DATE
Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti
2014 J jnl
XStat: Statistical
J. Low Power Electron.
Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti
2013 J jnl
An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test.
J. Low Power Electron.
Satya Trinadh, Seetal Potluri, Ch. Sobhan Babu, V. Kamakoti
2013 C conf
LPScan: An algorithm for supply scaling and switching activity minimization during test.
ICCD
Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran
2013 B conf
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information.
ETS
Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti
2012 J jnl
Interconnect Aware Test Power Reduction.
J. Low Power Electron.
Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti
2012 J jnl
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs.
J. Low Power Electron.
Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti
2011 — conf
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction.
ISVLSI
Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti