Sebastian Linnhoff

12 papers C 5Unranked 7

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 2×2 10GS/s TTD BF Receiver Utilizing Charge-Based Summation with 10.5GHz Bandwidth and SNDR/SFDR with 49.5dB/57.5dBc in 22nm CMOS. ISSCC Enne Wittenhagen, Dominik Wilding, Patrick J. Artz, Sebastian Linnhoff, Philipp Scholz, Friedel Gerfers
2025	C	`conf`	A Nyquist-rate 128 GS/s 6-Bit 64x Time-Interleaved SAR ADC in 22nm FD-SOI. ISCAS Christian Rudorf, Nima Lotfi, Sebastian Linnhoff, Enne Wittenhagen, Äantas Kesten, Friedel Gerfers
2024	C	`conf`	An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR. ISCAS Enne Wittenhagen, Dominik Wilding, Patrick Kurth, Sebastian Linnhoff, Frowin Buballa, Urs Hecht, Patrick J. Artz, Friedel Gerfers
2023	—	`conf`	A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold. NEWCAS Sebastian Linnhoff, Frowin Buballa, Julius Edler, Enne Wittenhagen, Urs Hecht, Friedel Gerfers
2023	—	`conf`	A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB \|THD\| and >49.3 dB SNDR in 22 nm FD-SOI CMOS. NEWCAS Enne Wittenhagen, Patrick Kurth, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Nima Lotfi, Friedel Gerfers
2023	—	`conf`	A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS. NEWCAS Frowin Buballa, Sebastian Linnhoff, Enne Wittenhagen, Urs Hecht, Friedel Gerfers
2023	—	`conf`	A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. VLSI Technology and Circuits Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers
2023	C	`conf`	A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling. ISCAS Patrick Kurth, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Helia Ordouei, Friedel Gerfers
2021	C	`conf`	A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. ISCAS Frowin Buballa, Sebastian Linnhoff, Michael Reinhold, Friedel Gerfers
2021	C	`conf`	A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. ISCAS Sebastian Linnhoff, Erik Sippel, Frowin Buballa, Michael Reinhold, Martin Vossiek, Friedel Gerfers
2020	—	`conf`	A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS. ICECS Sebastian Linnhoff, Frowin Buballa, Michael Reinhold, Friedel Gerfers
2018	—	`conf`	A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS. MWSCAS Marcel Runge, Sebastian Linnhoff, Friedel Gerfers