Sean Safarpour

31 papers A* 2A 10B 1C 1Journal 5Unranked 12
YearRankTypeTitle / Venue / Authors
2011 A conf
Automated debugging of SystemVerilog assertions.
DATE
Brian Keng, Sean Safarpour, Andreas G. Veneris
2011 A conf
Debugging with dominance: On-the-fly RTL debug solution implications.
ICCAD
Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour
2011 — conf
From RTL to silicon: The case for automated debug.
ASP-DAC
Andreas G. Veneris, Brian Keng, Sean Safarpour
2011 J jnl
Toward Automated ECOs in FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu
2010 — conf
An Automated Framework for Correction and Debug of PSL Assertions.
MTV
Brian Keng, Andreas G. Veneris, Sean Safarpour
2010 J jnl
Automated Design Debugging With Maximum Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris
2010 — conf
Automated silicon debug data analysis techniques for a hardware data acquisition environment.
ISQED
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour
2010 J jnl
Bounded Model Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Brian Keng, Sean Safarpour, Andreas G. Veneris
2010 — conf
Managing verification error traces with bounded model debugging.
ASP-DAC
Sean Safarpour, Andreas G. Veneris, Farid N. Najm
2009 J jnl
Automated Design Debugging With Abstraction and Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sean Safarpour, Andreas G. Veneris
2009 — conf
Automated debugging with high level abstraction and refinement.
HLDVT
Sean Safarpour, Andreas G. Veneris
2009 — conf
Spatial and temporal design debug using partial MaxSAT.
ACM Great Lakes Symposium on VLSI
Yibin Chen, Sean Safarpour, Andreas G. Veneris, João Marques-Silva
2009 A* conf
The day Sherlock Holmes decided to do EDA.
DAC
Andreas G. Veneris, Sean Safarpour
2009 A conf
Towards automated ECOs in FPGAs.
FPGA
Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
2008 J jnl
Improved SAT-based Reachability Analysis with Observability Don't Cares.
J. Satisf. Boolean Model. Comput.
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2007 A conf
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.
ICCAD
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith
2007 A conf
Abstraction and refinement techniques in automated design debugging.
DATE
Sean Safarpour, Andreas G. Veneris
2007 B conf
Improved Design Debugging Using Maximum Satisfiability.
FMCAD
Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah
2007 A conf
Maximum circuit activity estimation using pseudo-boolean satisfiability.
DATE
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
2007 — conf
Trace Compaction using SAT-based Reachability Analysis.
ASP-DAC
Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian
2006 — conf
Abstraction and Refinement Techniques in Automated Design Debugging.
MTV
Sean Safarpour, Andreas G. Veneris
2006 A* conf
Efficient SAT-based Boolean matching for FPGA technology mapping.
DAC
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan
2006 C conf
Integrating observability don't cares in all-solution SAT solvers.
ISCAS
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2006 A conf
On the relation between simulation-based and SAT-based diagnosis.
DATE
Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2005 — conf
Diagnosing multiple transition faults in the absence of timing information.
ACM Great Lakes Symposium on VLSI
Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
2005 — conf
Post-Verification Debugging of Hierarchical Designs.
MTV
Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005 A conf
Post-verification debugging of hierarchical designs.
ICCAD
Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005 — conf
Utilizing don't care states in SAT-based bounded sequential problems.
ACM Great Lakes Symposium on VLSI
Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
2004 — conf
Debugging Sequential Circuits Using Boolean Satisfiability.
MTV
Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith
2004 A conf
Debugging sequential circuits using Boolean satisfiability.
ICCAD
Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
2004 A conf
Managing Don't Cares in Boolean Satisfiability.
DATE
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee