Seamus Cawley

16 papers B 1C 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2018 C conf
Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC.
RSP
Fearghal Morgan, Declan O'Loughlin, Jeremy Audiger, Yohan Boyer, Niall Timlin-Canning, Krzysztof Kepa, Seamus Cawley, Ian Gallivan, László Bakó, Frank Callaly
2014 — conf
Exploring Neural Principles with Si elegans, a Neuromimetic Representation of the Nematode Caenorhabditis elegans.
NEUROTECHNIX
Axel W. Blau, Frank Callaly, Seamus Cawley, Aedan Coffey, Alessandro De Mauro, Gorka Epelde, Lorenzo Ferrara, Finn Krewer, Carlo Liberale, Pedro Machado, Gregory Maclair, Thomas Martin McGinnity, Fearghal Morgan, Andoni Mujika, Alexey Petrushin, Gautier Robin, John J. Wade
2014 — conf
The Si elegans Project - The Challenges and Prospects of Emulating Caenorhabditis elegans.
Living Machines
Axel W. Blau, Frank Callaly, Seamus Cawley, Aedan Coffey, Alessandro De Mauro, Gorka Epelde, Lorenzo Ferrara, Finn Krewer, Carlo Liberale, Pedro Machado, Gregory Maclair, Thomas Martin McGinnity, Fearghal Morgan, Andoni Mujika, Alessandro Petrushin, Gautier Robin, John J. Wade
2013 J jnl
Fixed latency on-chip interconnect for hardware spiking neural network architectures.
Parallel Comput.
Sandeep Pande, Fearghal Morgan, Gerard J. M. Smit, Tom M. Bruintjes, Jochem H. Rutgers, Brian McGinley, Seamus Cawley, Jim Harkin, Liam McDaid
2013 J jnl
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network.
Neural Process. Lett.
Sandeep Pande, Fearghal Morgan, Seamus Cawley, Tom M. Bruintjes, Gerard J. M. Smit, Brian McGinley, Snaider Carrillo, Jim Harkin, Liam McDaid
2013 J jnl
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations.
IEEE Trans. Parallel Distributed Syst.
Snaider Carrillo, Jim Harkin, Liam McDaid, Fearghal Morgan, Sandeep Pande, Seamus Cawley, Brian McGinley
2012 J jnl
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.
Neural Networks
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, Fearghal Morgan
2012 — conf
Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations.
NOCS
Snaider Carrillo, Jim Harkin, L. J. McDaid, Sandeep Pande, Seamus Cawley, Brian McGinley, Fearghal Morgan
2012 J jnl
Remote FPGA Lab for Enhancing Learning of Digital Systems.
ACM Trans. Reconfigurable Technol. Syst.
Fearghal Morgan, Seamus Cawley, David Newell
2011 — conf
Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations.
ICANN (1)
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Fearghal Morgan
2011 — conf
Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures.
IJCCI (NCTA)
Sandeep Pande, Fearghal Morgan, Seamus Cawley, Brian McGinley, Jim Harkin, Snaider Carrillo, Liam McDaid
2011 — conf
Enhancing learning of digital systems using a remote FPGA lab.
ReCoSoC
Fearghal Morgan, Seamus Cawley
2011 J jnl
Hardware spiking neural network prototyping and application.
Genet. Program. Evolvable Mach.
Seamus Cawley, Fearghal Morgan, Brian McGinley, Sandeep Pande, Liam McDaid, Snaider Carrillo, Jim Harkin
2011 B conf
Remote FPGA Lab with Interactive Control and Visualisation Interface.
FPL
Fearghal Morgan, Seamus Cawley, Frank Callaly, Shane Agnew, Patrick Rocke, Martin O'Halloran, Nina Drozd, Krzysztof Kepa, Brian McGinley
2010 — conf
EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures.
SoC
Sandeep Pande, Fearghal Morgan, Seamus Cawley, Brian McGinley, Snaider Carrillo, Jim Harkin, Liam McDaid
2009 J jnl
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks.
Int. J. Reconfigurable Comput.
Jim Harkin, Fearghal Morgan, Liam McDaid, Steve Hall, Brian McGinley, Seamus Cawley