Se-Joong Lee

20 papers A 2B 1C 2Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2009 J jnl
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC.
IEEE Trans. Very Large Scale Integr. Syst.
Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Se-Joong Lee, Hoi-Jun Yoo
2006 A conf
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
DATE
Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo
2006 J jnl
Low-power network-on-chip for high-performance SoC design.
IEEE Trans. Very Large Scale Integr. Syst.
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2005 — conf
A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.
ISCAS (3)
Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2005 — conf
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.
ISCAS (3)
Kwanho Kim, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo
2005 J jnl
Analysis and Implementation of Practical, Cost-Effective Networks on Chips.
IEEE Des. Test Comput.
Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo
2005 J jnl
Packet-switched on-chip interconnection network for system-on-chip applications.
IEEE Trans. Circuits Syst. II Express Briefs
Se-Joong Lee, Kangmin Lee, Seong-Jun Song, Hoi-Jun Yoo
2004 — conf
Low energy transmission coding for on-chip serial communications.
SoCC
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2004 — conf
On-chip network based embedded core testing.
SoCC
Jong-Sun Kim, Min-Su Hwang, Seungsu Roh, Ja-Young Lee, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2004 A conf
SILENT: serialized low energy transmission coding for on-chip interconnection networks.
ICCAD
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2003 — conf
A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer.
ESSCIRC
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2003 — conf
A distributed crossbar switch scheduler for on-chip networks.
CICC
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2003 — conf
A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks.
ESSCIRC
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2002 J jnl
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.
IEEE J. Solid State Circuits
Ramchan Woo, Chi-Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo
2002 B conf
A practical method to use eDRAM in the shared bus packet switch.
GLOBECOM
Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2002 J jnl
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth.
IEEE J. Solid State Circuits
Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo
2002 J jnl
Race logic architecture (RALA): a novel logic concept using the race scheme of input variables.
IEEE J. Solid State Circuits
Se-Joong Lee, Hoi-Jun Yoo
2001 J jnl
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications.
IEEE J. Solid State Circuits
Chi-Weon Yoon, Ramchan Woo, Jeengheon Kook, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yeo
2000 C conf
A 670 ps, 64 bit dynamic low-power adder design.
ISCAS
Ramchan Woo, Se-Joong Lee, Hoi-Jun Yoo
2000 C conf
One chip-low power digital-TCXO with sub-ppm accuracy.
ISCAS
Se-Joong Lee, Jinho Han, Seung-Ho Hank, Joe-Ho Lee, Jung-Su Kim, Minkyu Je, Hoi-Jun Yoo