Scott Lerner

16 papers A 1C 6Misc 1Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2024 C conf
Design Automation for Charge Recovery Logic.
ISCAS
Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin
2021 J jnl
Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano
2019 J jnl
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Scott Lerner, Isikcan Yilmaz, Baris Taskin
2019 C conf
Low Swing - Low Frequency Rotary Traveling Wave Oscillators.
ISCAS
Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin
2019 A conf
Robust Low Power Clock Synchronization for Multi-Die Systems.
ISLPED
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis
2019 J jnl
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Scott Lerner, Baris Taskin
2018 C conf
NoC Router Lifetime Improvement using Per-Port Router Utilization.
ISCAS
Scott Lerner, Vasil Pano, Baris Taskin
2018 — conf
Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis.
IGSC
Scott Lerner, Baris Taskin
2018 C conf
Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement.
ISCAS
Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin
2017 — conf
Slew-down: analysis of slew relaxation for low-impact clock buffers.
SLIP
Scott Lerner, Eric Leggett, Baris Taskin
2017 C conf
Stability of Rotary Traveling Wave Oscillators under process variations and NBTI.
ISCAS
Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin
2017 — conf
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS.
ISVLSI
Scott Lerner, Baris Taskin
2017 — conf
Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors.
ISQED
Scott Lerner, Baris Taskin
2015 Misc conf
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation.
VLSID
Siddharth Nilakantan, Scott Lerner, Mark Hempstead, Baris Taskin
2014 C conf
Timing characterization of clock buffers for clock tree synthesis.
ICCD
Can Sitik, Scott Lerner, Baris Taskin
2008 — conf
A High-Speed Optical Multi-Drop Bus for Computer Interconnections.
Hot Interconnects
Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals