Scott C. Smith

63 papers A 1C 4Misc 1Journal 25Unranked 31

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Approximate Memory for Low-Power Video Applications. IEEE Access Hritom Das, Ali Ahmad Haidous, Scott C. Smith, Na Gong
2023	J	`jnl`	Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits. IEEE Access Danylo Khodosevych, Alexander C. Bodoh, Ashiq A. Sakib, Scott C. Smith
2022	J	`jnl`	Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism. J. Electron. Test. Brett Sparkman, Scott C. Smith, Jia Di
2022	J	`jnl`	Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits. IET Comput. Digit. Tech. Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith, Nimish Mathure
2021	J	`jnl`	Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation. IEEE Trans. Very Large Scale Integr. Syst. Hritom Das, Ali Ahmad Haidous, Scott C. Smith, Na Gong
2021	J	`jnl`	Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT. IEEE Internet Things J. Jingyan Fu, Zhiheng Liao, Jianqing Liu, Scott C. Smith, Jinhui Wang
2021	—	`conf`	Security Threat Modeling for Power Transformers in Cyber-Physical Environments. ISGT BoHyun Ahn, Taesic Kim, Scott C. Smith, Young-Woo Youn, Myung-Hyo Ryu
2020	J	`jnl`	An Ancillary Services Model for Data Centers and Power Systems. IEEE Trans. Cloud Comput. Sahibzada Muhammad Ali, Muhammad Jawad, Muhammad Usman Shahid Khan, Kashif Bilal, Jacob Glower, Scott C. Smith, Samee U. Khan, Keqin Li, Albert Y. Zomaya
2020	Misc	`conf`	Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits. VTS Brett Sparkman, Scott C. Smith, Jia Di
2020	—	`conf`	Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits. MWSCAS Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith
2020	—	`conf`	Formal Verification of Completion-Completeness for NCL Circuits. MWSCAS Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith
2020	—	`conf`	Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit. MWSCAS Nauman Jalil, Scott C. Smith
2020	—	`conf`	Hardware Trojan Design and Detection in Asynchronous NCL Circuits. ICECS Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith
2020	—	`conf`	Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice. MWSCAS Ashiq A. Sakib, Abir A. Akib, Scott C. Smith
2020	—	`conf`	Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology. ICECS Ashiq A. Sakib, Scott C. Smith
2020	J	`jnl`	Performance optimization of rotation-tolerant Viola-Jones-based blackbird detection. J. Real Time Image Process. Nauman Jalil, Scott C. Smith, Roger Green
2019	C	`conf`	An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits. ISCAS Mousam Hossain, Ashiq A. Sakib, Sudarshan K. Srinivasan, Scott C. Smith
2019	J	`jnl`	Formal Modeling and Verification of PCHB Asynchronous Circuits. IEEE Trans. Very Large Scale Integr. Syst. Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
2018	—	`conf`	An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits. MWSCAS Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
2017	—	`conf`	An FPGA-in-the-loop approach for HDL motor controller verification. ReConFig Paul Rogers, Rajesh Kavasseri, Scott C. Smith
2017	—	`conf`	Analysis and design of CMOS resettable C-elements. MWSCAS Nasim Soufizadeh-Balaneji, Scott C. Smith
2017	—	`conf`	Formal modeling and verification for pre-charge half buffer gates and circuits. MWSCAS Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan
2016	—	`conf`	An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors. ReConFig Paul Rogers, Rajesh Kavasseri, Scott C. Smith
2016	J	`jnl`	Design for Testability of Sleep Convention Logic. IEEE Trans. Very Large Scale Integr. Syst. Farhad Alibeygi Parsan, Scott C. Smith, Waleed K. Al-Assadi
2014	C	`conf`	Equivalence verification for NULL Convention Logic (NCL) circuits. ICCD Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith
2014	J	`jnl`	Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. Farhad Alibeygi Parsan, Waleed K. Al-Assadi, Scott C. Smith
2014	—	`conf`	SCL design of a pipelined 8051 ALU. MWSCAS Farhad Alibeygi Parsan, J. Zhao, Scott C. Smith
2013	J	`jnl`	An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency. J. Low Power Electron. Michael Hinds, Brett Sparkman, Jia Di, Scott C. Smith
2013	J	`jnl`	Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic. Microelectron. J. Washington Cilio, Michael Linder, Chris Porter, Jia Di, Dale R. Thompson, Scott C. Smith
2013	—	`conf`	Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design. MWSCAS Pragadesh Varadharajan, Waleed K. Al-Assadi, Shabab F. Alam, Scott C. Smith
2013	—	`conf`	Sleep Convention Logic using partially slept function blocks. MWSCAS Parviz Palangpour, Scott C. Smith
2012	—	`conf`	CMOS Implementation of Threshold Gates with Hysteresis. VLSI-SoC (Selected Papers) Farhad Alibeygi Parsan, Scott C. Smith
2012	—	`conf`	CMOS implementation comparison of NCL gates. MWSCAS Farhad Alibeygi Parsan, Scott C. Smith
2012	C	`conf`	CMOS implementation of static threshold gates with hysteresis: A new approach. VLSI-SoC Farhad Alibeygi Parsan, Scott C. Smith
2012	—	`conf`	Uncle - An RTL Approach to Asynchronous Design. ASYNC Robert B. Reese, Scott C. Smith, Mitchell A. Thornton
2010	—	`conf`	Delay-Insensitive Cell Matrix. CDES Scott C. Smith, David Roclin, Jia Di
2010	J	`jnl`	Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum. IEEE Trans. Educ. Scott C. Smith, Waleed K. Al-Assadi, Jia Di
2009	—	`conf`	Delay-Insensitive Ternary Logic. CDES Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di
2009	—	`book`	Designing Asynchronous Circuits using NULL Convention Logic (NCL) Scott C. Smith, Jia Di
2009	—	`conf`	Integrated software-hardware design for ultra-low power infrastructure monitoring. ITSC Jingxian Wu, Scott C. Smith
2009	—	`conf`	Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith
2009	—	`conf`	Particle Swarm Optimization: A Hardware Implementation. CDES Parviz Palangpour, Ganesh K. Venayagamoorthy, Scott C. Smith
2008	J	`jnl`	Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. J. Low Power Electron. Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott C. Smith
2007	J	`jnl`	Automated energy calculation and estimation for delay-insensitive digital circuits. Microelectron. J. Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, Scott C. Smith
2007	J	`jnl`	DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith, Sindhu Kakarla
2007	A	`conf`	Design of a logic element for implementing an asynchronous FPGA. FPGA Scott C. Smith
2007	J	`jnl`	Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. Scott C. Smith
2007	J	`jnl`	Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits. Eng. Appl. Artif. Intell. Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav Singhal
2006	J	`jnl`	Speedup of NULL convention digital circuits using NULL cycle reduction. J. Syst. Archit. Scott C. Smith
2005	J	`jnl`	Development of a large word-width high-speed asynchronous multiply and accumulate unit. Integr. Scott C. Smith
2005	—	`conf`	High-Speed Energy Estimation for Delay-Insensitive Circuits. CDES Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith
2005	—	`conf`	Implementation of Design For Test for Asynchronous NCL Designs. CDES Bonita Bhaskaran, Venkat Satagopan, Waleed K. Al-Assadi, Scott C. Smith
2005	—	`conf`	Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. CDES Anshul Singh, Scott C. Smith
2004	—	`conf`	Design of a NULL Convention Self-Timed Divider. ESA/VLSI Scott C. Smith
2004	—	`conf`	Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. ESA/VLSI Scott C. Smith
2004	J	`jnl`	Optimization of NULL convention self-timed circuits. Integr. Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, Dennis Ferguson, D. Lamb
2003	—	`conf`	Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. VLSI Scott C. Smith
2003	—	`conf`	Design and Characterization of NULL Convention Arithmetic Logic Units. VLSI Satish K. Bandapati, Scott C. Smith
2003	J	`jnl`	Design and Characterization of Null Convention Self-Timed Multipliers. IEEE Des. Test Comput. Satish K. Bandapati, Scott C. Smith, Minsu Choi
2003	C	`conf`	On generating random systems: a gramian approach. ACC Scott C. Smith, James Fisher
2002	J	`jnl`	NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation. J. Syst. Archit. Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson
2002	—	`conf`	Speedup of Self-Timed Digital Systems Using Early Completion. ISVLSI Scott C. Smith
2001	J	`jnl`	Delay-insensitive gate-level pipelining. Integr. Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson