Sayak Ray

25 papers A* 4A 4B 3C 1Misc 2Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2024 Misc conf
Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS.
VLSID
Debayan Das, Majid Sabbagh, Rana Elnaggar, Guang Chen, Sayak Ray, Jason M. Fung
2023 J jnl
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.
IEEE Trans. Computers
Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
2023 A* conf
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK.
DAC
Anupam Golder, Debayan Das, Santosh Ghosh, Avinash Varna, Majid Sabbagh, Sayak Ray, Rana Elnaggar, Joseph Friel, Daniel Dinu, Jason M. Fung
2023 A conf
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL.
ICCAD
Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz
2022 A* conf
Automating hardware security property generation: invited.
DAC
Ryan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton
2021 J jnl
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.
CoRR
Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
2019 A* conf
Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs.
DAC
Sayak Ray, Nishant Ghosh, Ramya Jayaram Masti, Arun K. Kanuparthi, Jason M. Fung
2019 J jnl
Verification of Authenticated Firmware Load.
IACR Cryptol. ePrint Arch.
Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray
2019 B conf
Verification of Authenticated Firmware Loaders.
FMCAD
Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray
2018 A* conf
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware.
DAC
Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik
2017 A conf
Malware detection using machine learning based analysis of virtual memory access patterns.
DATE
Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik
2015 — conf
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies.
ASP-DAC
Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury
2015 — conf
Evaluating the security of logic encryption algorithms.
HOST
Pramod Subramanyan, Sayak Ray, Sharad Malik
2015 B conf
Template-based Synthesis of Instruction-Level Abstractions for SoC Verification.
FMCAD
Pramod Subramanyan, Yakir Vizel, Sayak Ray, Sharad Malik
2014 — conf
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification.
ASP-DAC
Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
2014 — conf
Effective abstraction for response proof of communication fabrics.
NOCS
Sayak Ray, Sharad Malik
2014 — conf
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract).
BCB
Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
2013 C conf
Ranking structure in communication fabrics.
MEMOCODE
Sayak Ray, Robert K. Brayton
2013 — —
Scalable Model Checking Beyond Safety - A Communication Fabric Perspective.
Sayak Ray
2012 J jnl
A dynamic assertion-based verification platform for validation of UML designs.
ACM SIGSOFT Softw. Eng. Notes
Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan
2012 A conf
Mapping into LUT structures.
DATE
Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen
2012 A conf
Scalable progress verification in credit-based flow-control systems.
DATE
Sayak Ray, Robert K. Brayton
2011 — conf
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models.
DIFTS@FMCAD
Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton
2008 B conf
A Dynamic Assertion-Based Verification Platform for Validation of UML Designs.
ATVA
Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan
2007 Misc conf
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.
VLSI Design
Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti