Savithri Sundareswaran

25 papers A* 4A 6Misc 2Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2019 J jnl
SLECTS: Slew-Driven Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang
2015 J jnl
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating.
ACM Trans. Design Autom. Electr. Syst.
Tong Xu, Peng Li, Savithri Sundareswaran
2011 — conf
A sensitivity-aware methodology to improve cell layouts for DFM guidelines.
ISQED
Savithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin
2010 — conf
Total sensitivity based dfm optimization of standard library cells.
ISPD
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
2009 — conf
Characterization of sequential cells for constraint sensitivities.
ISQED
Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal
2008 — conf
A timing methodology considering within-die clock skew variations.
SoCC
Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham
2008 — conf
Characterization of Standard Cells for Intra-Cell Mismatch Variations.
ISQED
Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda
2008 — conf
Faster statistical cell characterization using adjoint sensitivity analysis.
CICC
Ben Gu, Kiran K. Gullapalli, Yun Zhang, Savithri Sundareswaran
2008 A conf
Transistor-Specific Delay Modeling for SSTA.
DATE
Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran
2007 A conf
A novel technique for incremental analysis of on-chip power distribution networks.
ICCAD
Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao
2007 A conf
Analyzing the risk of timing modeling based on path delay tests.
ITC
Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir
2007 A* conf
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
DAC
Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
2007 — conf
Small-Delay Defect Detection in the Presence of Process Variations.
ISQED
Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham
2006 A* conf
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.
DAC
Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
2006 J jnl
Optimal placement of power-supply pads and pins.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2004 A* conf
A stochastic approach To power grid analysis.
DAC
Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2004 A* conf
Optimal placement of power supply pads and pins.
DAC
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2003 J jnl
Impact of Low-Impedance Substrate on Power Supply Integrity.
IEEE Des. Test Comput.
Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
2003 — conf
Statistical delay computation considering spatial correlations.
ASP-DAC
Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda
2003 A conf
Vectorless Analysis of Supply Noise Induced Delay Variation.
ICCAD
Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2002 J jnl
Slope propagation in static timing analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran
2001 A conf
On the interaction of power distribution network with substrate.
ISLPED
Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
2000 Misc conf
An Assertion Based Technique for Transistor Level Dynamic Power Estimation.
VLSI Design
Savithri Sundareswaran, R. Venkatesan, S. Bhaskar
2000 A conf
Slope Propagation in Static Timing Analysis.
ICCAD
David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
1999 Misc conf
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.
VLSI Design
Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury