Saurabh Sinha - RankMe

67 papers A* 10A 21C 2Journal 17Unranked 17

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2021	—	`conf`	3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. CICC Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni
2021	J	`jnl`	Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong
2021	J	`jnl`	High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. IEEE Trans. Very Large Scale Integr. Syst. Lingjun Zhu, Lennart Bamberg, Sai Surya Kiran Pentapati, Kyungwook Chang, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto García-Ortiz, Sung Kyu Lim
2020	—	`conf`	Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs. ISPD Lingjun Zhu, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, Sung Kyu Lim
2020	J	`jnl`	Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
2020	J	`jnl`	Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology. CoRR Rahul Mathur, Chien-Ju Chao, Rossana Liu, Nikhil Tadepalli, Pranavi Chandupatla, Shawn Hung, Xiaoqing Xu, Saurabh Sinha, Jaydeep P. Kulkarni
2019	A	`conf`	Enhanced 3D Implementation of an Arm ISLPED Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline
2019	J	`jnl`	System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2018	A*	`conf`	Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. DAC Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi
2018	J	`jnl`	Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. CoRR Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
2017	A	`conf`	Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017	A	`conf`	Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper). ICCAD Kyungwook Chang, Bon Woong Ku, Saurabh Sinha, Sung Kyu Lim
2017	J	`jnl`	Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. IEEE Trans. Very Large Scale Integr. Syst. Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017	J	`jnl`	Impact of FinFET on Near-Threshold Voltage Scalability. IEEE Des. Test Nathaniel Ross Pinckney, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw, Lucian Shifren, Brian Cline, Saurabh Sinha
2017	A	`conf`	Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). ICCAD Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
2016	J	`jnl`	ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
2016	A	`conf`	Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. ICCAD Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
2016	A	`conf`	Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. ISLPED Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016	J	`jnl`	Lessons from the tech transfer trenches. Commun. ACM Satish Chandra, Suresh Thummalapenta, Saurabh Sinha
2016	A*	`conf`	Match-making for monolithic 3D IC: finding the right technology node. DAC Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016	—	`conf`	Monolithic 3D IC design: Power, performance, and area impact at 7nm. ISQED Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2016	A*	`conf`	Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. DAC Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2016	J	`jnl`	Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric
2015	—	`conf`	Automated Modularization of GUI Test Cases. ICSE (1) Rahulkrishna Yandrapally, Giriprasad Sridhara, Saurabh Sinha
2015	—	`conf`	Circuit design perspectives for Ge FinFET at 10nm and beyond. ISQED Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov
2015	A	`conf`	Power benefit study of monolithic 3D IC at the 7nm technology node. ISLPED Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2015	A	`conf`	Test Generation from Business Rules. ICST Simon Holm Jensen, Suresh Thummalapenta, Saurabh Sinha, Satish Chandra
2014	J	`jnl`	Global software testing under deadline pressure: Vendor-side experiences. Inf. Softw. Technol. Hina Shah, Mary Jean Harrold, Saurabh Sinha
2014	—	`conf`	Operational abstractions of model transforms. ISEC Vibha Singhal Sinha, Pankaj Dhoolia, Senthil Mani, Saurabh Sinha
2014	—	`conf`	Physical design and FinFETs. ISPD Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra
2014	A	`conf`	Robust test automation using contextual clues. ISSTA Rahulkrishna Yandrapally, Suresh Thummalapenta, Saurabh Sinha, Satish Chandra
2014	—	`conf`	Software services: a research roadmap. FOSE Satish Chandra, Vibha Singhal Sinha, Saurabh Sinha, Krishna Ratakonda
2013	A*	`conf`	Efficient and change-resilient test automation: an industrial case study. ICSE Suresh Thummalapenta, Pranavadatta Devaki, Saurabh Sinha, Satish Chandra, Sivagami Gnanasundaram, Deepa D. Nagaraj, Sampathkumar Sathishkumar
2013	A*	`conf`	Guided test generation for web applications. ICSE Suresh Thummalapenta, K. Vasanta Lakshmi, Saurabh Sinha, Nishant Sinha, Satish Chandra
2013	—	`conf`	The past present and future of design-technology co-optimization. CICC Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken
2012	A*	`conf`	Automating test automation. ICSE Suresh Thummalapenta, Saurabh Sinha, Nimit Singhania, Satish Chandra
2012	A	`conf`	Design benchmarking to 7nm with FinFET predictive technology models. ISLPED Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
2012	—	`conf`	Efficiently scripting change-resilient tests. SIGSOFT FSE Suresh Thummalapenta, Nimit Singhania, Pranavadatta Devaki, Saurabh Sinha, Satish Chandra, Achin K. Das, Srinivas Mangipudi
2012	A*	`conf`	Exploring sub-20nm FinFET design with predictive technology models. DAC Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao
2011	—	`conf`	A workload-aware neuromorphic controller for dynamic power and thermal management. AHS Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao
2011	A	`conf`	Entering the circle of trust: developer initiation as committers in open-source projects. MSR Vibha Singhal Sinha, Senthil Mani, Saurabh Sinha
2011	C	`conf`	Outsourced, Offshored Software-Testing Practice: Vendor-Side Experiences. ICGSE Hina Shah, Saurabh Sinha, Mary Jean Harrold
2011	A	`conf`	Serving Information Needs in Business Process Consulting. BPM Monika Gupta, Debdoot Mukherjee, Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha
2011	J	`jnl`	Workload-Aware Neuromorphic Design of the Power Controller. IEEE J. Emerg. Sel. Topics Circuits Syst. Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao
2010	A	`conf`	Automated Bug Neighborhood Analysis for Identifying Incomplete Bug Fixes. ICST Mijung Kim, Saurabh Sinha, Carsten Görg, Hina Shah, Mary Jean Harrold, Mangala Gowri Nanda
2010	A*	`conf`	Automated support for repairing input-model faults. ASE Senthil Mani, Vibha Singhal Sinha, Pankaj Dhoolia, Saurabh Sinha
2010	—	`conf`	BUGINNINGS: identifying the origins of a bug. ISEC Vibha Singhal Sinha, Saurabh Sinha, Swathi Rao
2010	A	`conf`	Debugging Model-Transformation Failures Using Dynamic Tainting. ECOOP Pankaj Dhoolia, Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha
2010	A	`conf`	From Informal Process Diagrams to Formal Process Models. BPM Debdoot Mukherjee, Pankaj Dhoolia, Saurabh Sinha, Aubrey J. Rembert, Mangala Gowri Nanda
2010	—	`conf`	Making defect-finding tools work for you. ICSE (2) Mangala Gowri Nanda, Monika Gupta, Saurabh Sinha, Satish Chandra, David Schmidt, Pradeep Balachandran
2010	A	`conf`	Workload-aware neuromorphic design of low-power supply voltage controller. ISLPED Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao
2009	A*	`conf`	Accurate Interprocedural Null-Dereference Analysis for Java. ICSE Mangala Gowri Nanda, Saurabh Sinha
2009	A	`conf`	Demystifying model transformations: an approach based on automated rule inference. OOPSLA Mangala Gowri Nanda, Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha
2009	A	`conf`	Efficient Testing of Service-Oriented Applications Using Semantic Service Stubs. ICWS Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha, Pankaj Dhoolia, Debdoot Mukherjee, Soham Chakraborty
2009	C	`conf`	Enabling resonant clock distribution with scaled on-chip magnetic inductors. ICCD Saurabh Sinha, Wei Xu, Jyothi Bhaskarr Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu, Yu Cao
2009	A	`conf`	Fault localization and repair for Java runtime exceptions. ISSTA Saurabh Sinha, Hina Shah, Carsten Görg, Shujuan Jiang, Mijung Kim, Mary Jean Harrold
2009	J	`jnl`	The Predictive Technology Model in the Late Silicon Era and Beyond. Found. Trends Electron. Des. Autom. Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao
2008	—	`conf`	A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. ISQED Saurabh Sinha, Asha Balijepalli, Yu Cao
2007	A	`conf`	Compact modeling of carbon nanotube transistor for early stage process-design exploration. ISLPED Asha Balijepalli, Saurabh Sinha, Yu Cao
2006	—	`conf`	Subsumption of program entities for efficient coverage and monitoring. SOQUA Raúl A. Santelices, Saurabh Sinha, Mary Jean Harrold
2001	J	`jnl`	Interprocedural control dependence. ACM Trans. Softw. Eng. Methodol. Saurabh Sinha, Mary Jean Harrold, Gregg Rothermel
2000	J	`jnl`	Analysis and Testing of Programs with Exception Handling Constructs. IEEE Trans. Software Eng. Saurabh Sinha, Mary Jean Harrold
1999	—	`conf`	Criteria for Testing Exception-Handling Constructs in Java Programs. ICSM Saurabh Sinha, Mary Jean Harrold
1999	A*	`conf`	System-Dependence-Graph-Based Slicing of Programs with Arbitrary Interprocedural Control Flow. ICSE Saurabh Sinha, Mary Jean Harrold, Gregg Rothermel
1998	—	`conf`	Analysis of Programs with Exception-Handling Constructs. ICSM Saurabh Sinha, Mary Jean Harrold
1998	A	`conf`	Computation of Interprocedural Control Dependence. ISSTA Mary Jean Harrold, Gregg Rothermel, Saurabh Sinha