Saurabh Saxena

74 papers A* 9C 4Misc 5Journal 39Unranked 16

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	360Anything: Geometry-Free Lifting of Images and Videos to 360°. CoRR Ziyi Wu, Daniel Watson, Andrea Tagliasacchi, David J. Fleet, Marcus A. Brubaker, Saurabh Saxena
2026	Misc	`conf`	A 2.95 pJ/b 42Gb/s PAM-8 Clock and Data Recovery. VLSID Saurabh Saxena, Neel Hingrajiya, Suryadipto Mukherjee, Vivek Pala
2026	Misc	`conf`	A 8-16 Gb/s/pin Full-Duplex Voltage-Mode Transmitter with Pulse Width Modulation Based Equalization and Analog Echo Canceller. VLSID Saurabh Saxena, Vinod Ganesan, Shubham Choudhary
2025	A*	`conf`	Controlling Space and Time with Diffusion Models. ICLR Daniel Watson, Saurabh Saxena, Lala Li, Andrea Tagliasacchi, David J. Fleet
2025	A*	`conf`	High-Resolution Frame Interpolation with Patch-based Cascaded Diffusion. AAAI Junhwa Hur, Charles Herrmann, Saurabh Saxena, Janne Kontkanen, Wei-Sheng Lai, Yichang Shih, Michael Rubinstein, David J. Fleet, Deqing Sun
2024	J	`jnl`	A 5.4-7.4 GHz Ultra-Low Jitter Injection-Locked Frequency Tripler With 3rd Harmonic Current Boosting Input Buffer. IEEE Trans. Circuits Syst. II Express Briefs Sonam Sadhukhan, Arpan Thakkar, Pranav Kumar, Saurabh Saxena
2024	J	`jnl`	Controlling Space and Time with Diffusion Models. CoRR Daniel Watson, Saurabh Saxena, Lala Li, Andrea Tagliasacchi, David J. Fleet
2024	J	`jnl`	High-Resolution Frame Interpolation with Patch-based Cascaded Diffusion. CoRR Junhwa Hur, Charles Herrmann, Saurabh Saxena, Janne Kontkanen, Wei-Sheng Lai, Yichang Shih, Michael Rubinstein, David J. Fleet, Deqing Sun
2024	A*	`conf`	NeRFiller: Completing Scenes via Generative 3D Inpainting. CVPR Ethan Weber, Aleksander Holynski, Varun Jampani, Saurabh Saxena, Noah Snavely, Abhishek Kar, Angjoo Kanazawa
2024	J	`jnl`	Optimizing Bug Resolution: A Data-Driven Developer Recommendation System. Int. J. Perform. Eng. Saurabh Saxena, Chetna Gupta
2024	J	`jnl`	RoMo: Robust Motion Segmentation Improves Structure from Motion. CoRR Lily Goli, Sara Sabour, Mark J. Matthews, Marcus A. Brubaker, Dmitry Lagun, Alec Jacobson, David J. Fleet, Saurabh Saxena, Andrea Tagliasacchi
2023	—	`conf`	A 0.49-9.8 Gb/s 0.1-1V Output Swing Transmitter with 38.4MHz Reference and <30 ns Turn-On Time. ESSCIRC Jaya Deepthi Bandarupalli, Saurabh Saxena
2023	Misc	`conf`	A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS. VLSID Shivam Nigam, Mukund Murali, Hari Shanker Gupta, Saurabh Saxena
2023	Misc	`conf`	A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications. VLSID Snigdha Jakkoju, Deepthi J. Bandarupalli, Anil Srikanth, Saji Thomas, Saurabh Saxena
2023	A*	`conf`	A Generalist Framework for Panoptic Segmentation of Images and Videos. ICCV Ting Chen, Lala Li, Saurabh Saxena, Geoffrey E. Hinton, David J. Fleet
2023	J	`jnl`	Monocular Depth Estimation using Diffusion Models. CoRR Saurabh Saxena, Abhishek Kar, Mohammad Norouzi, David J. Fleet
2023	J	`jnl`	NeRFiller: Completing Scenes via Generative 3D Inpainting. CoRR Ethan Weber, Aleksander Holynski, Varun Jampani, Saurabh Saxena, Noah Snavely, Abhishek Kar, Angjoo Kanazawa
2023	A*	`conf`	The Surprising Effectiveness of Diffusion Models for Optical Flow and Monocular Depth Estimation. NeurIPS Saurabh Saxena, Charles Herrmann, Junhwa Hur, Abhishek Kar, Mohammad Norouzi, Deqing Sun, David J. Fleet
2023	J	`jnl`	The Surprising Effectiveness of Diffusion Models for Optical Flow and Monocular Depth Estimation. CoRR Saurabh Saxena, Charles Herrmann, Junhwa Hur, Abhishek Kar, Mohammad Norouzi, Deqing Sun, David J. Fleet
2023	J	`jnl`	Zero-Shot Metric Depth with a Field-of-View Conditioned Diffusion Model. CoRR Saurabh Saxena, Junhwa Hur, Charles Herrmann, Deqing Sun, David J. Fleet
2022	J	`jnl`	A 1.12-1.91 mW/GHz 2.46-4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS. IEEE J. Solid State Circuits R. Gautam, Saurabh Saxena
2022	J	`jnl`	A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUI IEEE Trans. Circuits Syst. II Express Briefs Jaya Deepthi Bandarupalli, Saurabh Saxena
2022	Misc	`conf`	A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer. VLSID Shraman Mukherjee, Sumantra Seth, Saurabh Saxena
2022	C	`conf`	A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process. ISCAS Sonam Sadhukhan, Pranav Kumar, Arpan Thakkar, Apoorva Bhatia, Saurabh Saxena
2022	J	`jnl`	A Generalist Framework for Panoptic Segmentation of Images and Videos. CoRR Ting Chen, Lala Li, Saurabh Saxena, Geoffrey E. Hinton, David J. Fleet
2022	J	`jnl`	A Surface Energy Balance Model for Predicting Temperature Evolution of Random-Shaped Smoldering Objects in Open Environments. CoRR Saurabh Saxena, Neda Yaghoobian
2022	A*	`conf`	A Unified Sequence Interface for Vision Tasks. NeurIPS Ting Chen, Saurabh Saxena, Lala Li, Tsung-Yi Lin, David J. Fleet, Geoffrey E. Hinton
2022	J	`jnl`	A Unified Sequence Interface for Vision Tasks. CoRR Ting Chen, Saurabh Saxena, Lala Li, Tsung-Yi Lin, David J. Fleet, Geoffrey E. Hinton
2022	A*	`conf`	Photorealistic Text-to-Image Diffusion Models with Deep Language Understanding. NeurIPS Chitwan Saharia, William Chan, Saurabh Saxena, Lala Li, Jay Whang, Emily L. Denton, Seyed Kamyar Seyed Ghasemipour, Raphael Gontijo Lopes, Burcu Karagol Ayan, Tim Salimans, Jonathan Ho, David J. Fleet, Mohammad Norouzi
2022	J	`jnl`	Photorealistic Text-to-Image Diffusion Models with Deep Language Understanding. CoRR Chitwan Saharia, William Chan, Saurabh Saxena, Lala Li, Jay Whang, Emily Denton, Seyed Kamyar Seyed Ghasemipour, Burcu Karagol Ayan, S. Sara Mahdavi, Raphael Gontijo Lopes, Tim Salimans, Jonathan Ho, David J. Fleet, Mohammad Norouzi
2022	A*	`conf`	Pix2seq: A Language Modeling Framework for Object Detection. ICLR Ting Chen, Saurabh Saxena, Lala Li, David J. Fleet, Geoffrey E. Hinton
2021	J	`jnl`	A Machine Learning Degradation Model for Electrochemical Capacitors Operated at High Temperature. IEEE Access Darius Roman, Saurabh Saxena, Jens Bruns, Valentin Robu, Michael G. Pecht, David Flynn
2021	J	`jnl`	Machine learning pipeline for battery state of health estimation. CoRR Darius Roman, Saurabh Saxena, Valentin Robu, Michael G. Pecht, David Flynn
2021	J	`jnl`	Machine learning pipeline for battery state-of-health estimation. Nat. Mach. Intell. Darius Roman, Saurabh Saxena, Valentin Robu, Michael G. Pecht, David Flynn
2021	J	`jnl`	Pix2seq: A Language Modeling Framework for Object Detection. CoRR Ting Chen, Saurabh Saxena, Lala Li, David J. Fleet, Geoffrey E. Hinton
2020	C	`conf`	A 2.5-5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS. ISCAS R. Gautam, Jaya Deepthi Bandarupalli, Saurabh Saxena
2020	J	`jnl`	An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer. IEEE Trans. Circuits Syst. II Express Briefs Shraman Mukherjee, Ashish Das, Sumantra Seth, Saurabh Saxena
2020	J	`jnl`	Analysis of Specified Capacity in Power Banks. IEEE Access Weiping Diao, Saurabh Saxena, Michael G. Pecht
2020	—	`conf`	Non-Autoregressive Machine Translation with Latent Alignments. EMNLP (1) Chitwan Saharia, William Chan, Saurabh Saxena, Mohammad Norouzi
2020	J	`jnl`	Non-Autoregressive Machine Translation with Latent Alignments. CoRR Chitwan Saharia, William Chan, Saurabh Saxena, Mohammad Norouzi
2019	—	`conf`	Quantifying the Impact of Prognostic Distance on Average Cost per Cycle. ICPHM Saikath Bhattacharya, Lance Fiondella, Saurabh Saxena, Michael G. Pecht
2019	J	`jnl`	The Explosive Nature of Tab Burrs in Li-Ion Batteries. IEEE Access Xingyan Yao, Saurabh Saxena, Lei Su, Michael G. Pecht
2018	—	`conf`	Anomaly Detection During Lithium-ion Battery Qualification Testing. ICPHM Saurabh Saxena, Myeongsu Kang, Yinjiao Xing, Michael G. Pecht
2018	C	`conf`	Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier. ISCAS Qadeer A. Khan, Saurabh Saxena, Abirmoya Santra
2018	J	`jnl`	Exploding E-Cigarettes: A Battery Safety Issue. IEEE Access Saurabh Saxena, Lingxi Kong, Michael G. Pecht
2018	J	`jnl`	Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. IEEE J. Solid State Circuits Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
2017	—	`conf`	29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
2017	J	`jnl`	A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu
2017	J	`jnl`	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	J	`jnl`	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	A*	`conf`	Large-Scale Evolution of Image Classifiers. ICML Esteban Real, Sherry Moore, Andrew Selle, Saurabh Saxena, Yutaka I. Leon-Suematsu, Jie Tan, Quoc V. Le, Alexey Kurakin
2017	J	`jnl`	Large-Scale Evolution of Image Classifiers. CoRR Esteban Real, Sherry Moore, Andrew Selle, Saurabh Saxena, Yutaka I. Leon-Suematsu, Quoc V. Le, Alex Kurakin
2016	—	`conf`	23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
2016	J	`jnl`	A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
2016	J	`jnl`	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. ISSCC Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
2015	—	`conf`	A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. IEEE J. Solid State Circuits Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`—`	Architectural & circuit level techniques to improve energy efficiency of high speed serial links Saurabh Saxena
2014	—	`conf`	15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. ISSCC Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu
2014	—	`conf`	8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2014	J	`jnl`	A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. IEEE J. Solid State Circuits Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
2014	J	`jnl`	A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2013	—	`conf`	A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. CICC Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
2012	J	`jnl`	A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2012	J	`jnl`	A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. IEEE Trans. Circuits Syst. I Regul. Pap. Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
2011	—	`conf`	A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. CICC Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
2011	—	`conf`	A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2010	J	`jnl`	Rapid-Thermal Annealing of Amorphous Silicon on Oxide Semiconductors. IEICE Trans. Electron. Saurabh Saxena, Jin Jang
2009	C	`conf`	Automatic Tuning of Time Constants in Single Bit Continuous-time Delta-sigma Modulators. ISCAS Saurabh Saxena, Prabu Sankar, Shanthi Pavan