Saurabh Kotiyal

12 papers A 1Misc 2Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
2016 J jnl
Design Methodologies for Reversible Logic Based Barrel Shifters.
J. Circuits Syst. Comput.
Saurabh Kotiyal, Himanshu Thapliyal
2015 J jnl
Reversible logic based multiplication computing unit using binary tree data structure.
J. Supercomput.
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 Misc conf
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits.
VLSID
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 J jnl
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain.
Trans. Comput. Sci.
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 J jnl
Efficient reversible NOR gates and their mapping in optical computing domain.
Microelectron. J.
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2014 — ch.
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits.
Field-Coupled Nanocomputing
Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
2013 J jnl
Design of Testable Reversible Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
2012 — conf
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates.
ISVLSI
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2012 A conf
Mach-Zehnder interferometer based design of all optical reversible binary adder.
DATE
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
2006 J jnl
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
CoRR
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
2006 Misc conf
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
VLSI Design
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
2005 — conf
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.
CSC
Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia