Satyanand Nalam

16 papers A* 1A 2C 1Misc 1Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2019 J jnl
A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications.
IEEE J. Solid State Circuits
Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl
2018 — conf
A 23.6Mb/mm
ISSCC
Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl
2017 J jnl
5.6 Mb/mm
IEEE J. Solid State Circuits
Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2016 — conf
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.
ISSCC
John Keane, Jaydeep P. Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2016 J jnl
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.
IEEE J. Solid State Circuits
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang
2015 — conf
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.
ISSCC
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang
2014 Misc conf
Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories.
VLSID
Sudhanshu Khanna, Satyanand Nalam, Benton H. Calhoun
2011 J jnl
5T SRAM With Asymmetric Sizing for Improved Read Stability.
IEEE J. Solid State Circuits
Satyanand Nalam, Benton H. Calhoun
2011 A conf
Dynamic write limited minimum operating voltage for nanoscale SRAMs.
DATE
Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun
2010 — conf
Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.
ISQED
Satyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun
2010 — conf
Improving SRAM Vmin and yield by using variation-aware BTI stress.
CICC
Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun
2010 — conf
Limits of bias based assist methods in nano-scale 6T SRAM.
ISQED
Randy W. Mann, Satyanand Nalam, Jiajing Wang, Benton H. Calhoun
2010 A* conf
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.
DAC
Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun
2009 C conf
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.
ICCD
Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun
2009 — conf
Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T.
CICC
Satyanand Nalam, Benton H. Calhoun
2008 A conf
Analyzing static and dynamic write margin for nanometer SRAMs.
ISLPED
Jiajing Wang, Satyanand Nalam, Benton H. Calhoun