Satoshi Takaya

21 papers C 1Journal 11Unranked 9
YearRankTypeTitle / Venue / Authors
2026 — conf
19.4 A Digital-Feedback Active-Gate-Driver IC for 600A 1200V SiC MOSFETs Supporting High-and Low-Side Drive with Simultaneous ${\text{dV}}_{\text{ds}}$/dt Control and ${\mathrm{V}}_{\text{ds}}$ Surge Suppression Enabled by Miller Capacitance Calibration.
ISSCC
Shusuke Kawai, Kohei Horii, Koutaro Miyazaki, Yuto Bushimata, Satoshi Takaya, Hiroaki Ishihara
2020 — conf
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics.
ISSCC
Satoshi Takaya, Hiroaki Ishihara, Kohei Onizuka
2019 — conf
Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications.
VLSI Circuits
Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami
2018 C conf
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays.
ISCAS
Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi
2018 J jnl
SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation.
IEICE Electron. Express
Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama
2017 J jnl
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
2017 J jnl
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology.
CoRR
Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani
2017 J jnl
SPICE Simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation.
CoRR
Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama
2016 — conf
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
ISSCC
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
2016 J jnl
Physically Unclonable Function using Initial Waveform of Ring Oscillators.
CoRR
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
2015 — conf
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.
ISSCC
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
2015 J jnl
In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking.
IEEE Des. Test
Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda
2014 — conf
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
ISSCC
Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
2014 J jnl
Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking.
IEICE Trans. Electron.
Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata
2013 — conf
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing.
ISSCC
Satoshi Takaya, Makoto Nagata, Atsushi Sakai, Takashi Kariya, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda
2013 J jnl
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation.
IEICE Trans. Electron.
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2013 — conf
Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs.
3DIC
Satoshi Takaya, Makoto Nagata, Hiroaki Ikeda
2012 J jnl
On-Chip In-Place Measurements of V
IEICE Trans. Electron.
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 J jnl
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits.
IEICE Trans. Electron.
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 — conf
Accurate analysis of substrate sensitivity of active transistors in an analog circuit.
ISQED
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011 J jnl
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement.
IEICE Trans. Electron.
Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata